From ef742f8f19c3c7c05e904d5a7f35bbe34e293a6c Mon Sep 17 00:00:00 2001
From: logicog <git@logicog.de>
Date: Sun, 24 Aug 2025 19:25:29 +0200
Subject: [PATCH] Cleanup and fix flushing of L2 UC entries

---
 rtl837x_common.h |  5 +++++
 rtl837x_port.c   | 40 ++++++++++++++++++++--------------------
 rtl837x_regs.h   |  5 ++++-
 3 files changed, 29 insertions(+), 21 deletions(-)

diff --git a/rtl837x_common.h b/rtl837x_common.h
index c536253..c8a0417 100644
--- a/rtl837x_common.h
+++ b/rtl837x_common.h
@@ -7,6 +7,11 @@
 // This has to be set to the number of SFP+ ports, i.e. 1 or 2
 #define NSFP 2
 
+// Define Port-masks for 9-port devices and 6-port devices
+#define PMASK_9		0x1ff
+#define PMASK_6		0x1f8
+#define PMASK_CPU	0x200
+
 // The serial buffer. Defines the command line size
 // Must be 2^x and <= 128
 #define SBUF_SIZE 128
diff --git a/rtl837x_port.c b/rtl837x_port.c
index beebc9d..4f183a7 100644
--- a/rtl837x_port.c
+++ b/rtl837x_port.c
@@ -253,19 +253,21 @@ void trunk_set(uint8_t group, uint16_t mask) __banked
 uint8_t port_l2_forget(void) __banked
 {
 	print_string("\nport_l2_forget called\n");
-	// r53dc:00000000 R53dc-00000000 r53d4:000001ff r53d4:000001ff R53d4-000101ff r53d4:000001ff
-	reg_read_m(0x53dc);
-	if (sfr_data[0] || sfr_data[1] ||sfr_data[2] ||sfr_data[3]) {
-		print_string("List busy\n");
-		return 0xff;
-	}
-	REG_WRITE(0x53dc, sfr_data[0], sfr_data[1], sfr_data[2], sfr_data[3]);
+	// Configure the entries to be flushed:
+	// port-based (bits 0-1 are 0 and dynamic entries, bit 2 specifies dynamic entries
+	REG_SET(RTL837x_L2_TBL_FLUSH_CNF, 0x0);
 
-	reg_read_m(RTL837x_L2_TBL_CTRL);
-	REG_WRITE(RTL837x_L2_TBL_CTRL, 0x00, 0x01, sfr_data[2], sfr_data[3]);
+	// Flush L2 table for all ports by setting the ports and the flush-exec bit (bit 16)
+	if (isRTL8373) {
+		REG_SET(RTL837x_L2_TBL_FLUSH_CTRL, L2_TBL_FLUSH_EXEC | PMASK_9);
+	} else {
+		REG_SET(RTL837x_L2_TBL_FLUSH_CTRL, L2_TBL_FLUSH_EXEC | PMASK_6);
+	}
+
+	// Wait for flush completed
 	do {
-		reg_read_m(RTL837x_L2_TBL_CTRL);
-	} while (sfr_data[1] & 0x1);
+		reg_read_m(RTL837x_L2_TBL_FLUSH_CTRL);
+	} while (sfr_data[1]);
 
 	print_string("port_l2_forget done\n");
 	return 0;
@@ -345,21 +347,19 @@ void port_l2_learned(void) __banked
 void port_l2_setup() __banked
 {
 	print_string("\nport_l2_setup called\n");
-	REG_SET(0x53dc, 0x00000000);
-	if(isRTL8373) {
-		REG_SET(0x53d4, 0x000101ff);
-	} else {
-		REG_SET(0x53d4, 0x000001f8);
-	}
+
+	port_l2_forget();
+
 	for (uint8_t i = minPort; i <= maxPort; i++) {
 		uint16_t reg = 0x5384 + (i << 2);
 		REG_SET(reg, 0x00001040);
 
-		reg = 0x50c0  + (i << 2);
+		// All ports may communicate with each other and CPU-Port
+		reg = RTL837X_PORT_ISOLATION_BASE + (i << 2);
 		if(isRTL8373) {
-			REG_SET(reg, 0x3ff);
+			REG_SET(reg, PMASK_9 | PMASK_CPU);
 		} else {
-			REG_SET(reg, 0x3f8);
+			REG_SET(reg, PMASK_6 | PMASK_CPU);
 		}
 	}
 	reg_bit_set(0x4f80, 0);
diff --git a/rtl837x_regs.h b/rtl837x_regs.h
index 24202ca..608643a 100644
--- a/rtl837x_regs.h
+++ b/rtl837x_regs.h
@@ -105,9 +105,12 @@
 #define RTL837x_L2_DATA_OUT_B	0x5cd0
 #define RTL837x_L2_DATA_OUT_C	0x5cd4
 #define RTL837x_TBL_DATA_IN_A	0x5cb8
-#define RTL837x_L2_TBL_CTRL	0x53d4
 #define RTL837x_PVID_BASE_REG	0x4e1c
 
+#define RTL837x_L2_TBL_FLUSH_CTRL	0x53d4
+#define L2_TBL_FLUSH_EXEC	0x10000
+#define RTL837x_L2_TBL_FLUSH_CNF	0x53dc
+
 /*
  * Egress / ingress filtering
  */