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https://github.com/logicog/RTLPlayground.git
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stp: drop the bounds on the L2 flush and L2MC table waits
The review asked for these to come out and the reasoning holds. A guard that gives up mid-transaction lets the code carry on with whatever the engine left behind, and that is what cost me an SPI clip twice. An unbounded wait on a wedged engine still hangs, but it hangs in a known place instead of writing garbage into the L2 table. BANK1 loses 45 bytes and xdata one. BANK2 and the common bank do not move.
This commit is contained in:
+3
-8
@@ -28,8 +28,6 @@ extern __xdata struct machine_runtime machine_detected;
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__xdata uint32_t l2_head;
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__xdata uint32_t l2_head;
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__xdata uint8_t l2mc_guard;
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__xdata struct vlan_settings vlan_settings;
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__xdata struct vlan_settings vlan_settings;
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void port_mirror_set(register uint8_t port, __xdata uint16_t rx_pmask, __xdata uint16_t tx_pmask) __banked
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void port_mirror_set(register uint8_t port, __xdata uint16_t rx_pmask, __xdata uint16_t tx_pmask) __banked
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@@ -324,10 +322,9 @@ void port_l2_forget_port(uint8_t port) __banked
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REG_SET(RTL837x_L2_TBL_FLUSH_CNF, 0x0); /* port-based, dynamic entries */
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REG_SET(RTL837x_L2_TBL_FLUSH_CNF, 0x0); /* port-based, dynamic entries */
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REG_SET(RTL837x_L2_TBL_FLUSH_CTRL, L2_TBL_FLUSH_EXEC | (((uint16_t)1) << port));
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REG_SET(RTL837x_L2_TBL_FLUSH_CTRL, L2_TBL_FLUSH_EXEC | (((uint16_t)1) << port));
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l2mc_guard = 0;
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do {
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do {
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reg_read_m(RTL837x_L2_TBL_FLUSH_CTRL);
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reg_read_m(RTL837x_L2_TBL_FLUSH_CTRL);
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} while (sfr_data[1] && ++l2mc_guard);
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} while (sfr_data[1]);
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}
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}
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@@ -426,19 +423,17 @@ void port_l2_learned(void) __banked
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void port_l2mc_set(uint8_t mac_last, __xdata uint16_t vid, __xdata uint16_t pmask) __banked
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void port_l2mc_set(uint8_t mac_last, __xdata uint16_t vid, __xdata uint16_t pmask) __banked
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{
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{
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l2mc_guard = 0;
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do {
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do {
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reg_read_m(RTL837X_TBL_CTRL);
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reg_read_m(RTL837X_TBL_CTRL);
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} while ((sfr_data[3] & TBL_EXECUTE) && ++l2mc_guard);
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} while (sfr_data[3] & TBL_EXECUTE);
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REG_WRITE(RTL837x_TBL_DATA_IN_A, 0xc2, 0x00, 0x00, mac_last);
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REG_WRITE(RTL837x_TBL_DATA_IN_A, 0xc2, 0x00, 0x00, mac_last);
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REG_WRITE(RTL837x_TBL_DATA_IN_B, 0x20 | (vid >> 8) | ((pmask & 0x3) << 6), vid, 0x01, 0x80);
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REG_WRITE(RTL837x_TBL_DATA_IN_B, 0x20 | (vid >> 8) | ((pmask & 0x3) << 6), vid, 0x01, 0x80);
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REG_WRITE(RTL837x_TBL_DATA_IN_C, 0, 0, 0, pmask >> 2);
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REG_WRITE(RTL837x_TBL_DATA_IN_C, 0, 0, 0, pmask >> 2);
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REG_WRITE(RTL837X_TBL_CTRL, 0, 0, TBL_L2_UNICAST, TBL_WRITE | TBL_EXECUTE);
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REG_WRITE(RTL837X_TBL_CTRL, 0, 0, TBL_L2_UNICAST, TBL_WRITE | TBL_EXECUTE);
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l2mc_guard = 0;
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do {
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do {
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reg_read_m(RTL837X_TBL_CTRL);
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reg_read_m(RTL837X_TBL_CTRL);
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} while ((sfr_data[3] & TBL_EXECUTE) && ++l2mc_guard);
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} while (sfr_data[3] & TBL_EXECUTE);
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}
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}
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