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stp: name the port count instead of spelling out ten
Review of #397 pointed at the bare 10, which shows up in fifteen places. It is the width of the port field in the MSTP register, so it is the CPU port index plus one and it gets a name. The web page counted to ten as well when listing a group's members. It uses numPorts now, like the rest of that page does. The aggregation section of the doc no longer names the OEM firmware or calls a group a trunk, and it says plainly that the hardware keeps no per-group state, so the firmware writes the members itself. Generated code is unchanged: the only difference in the assembly is the version string.
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+15
-11
@@ -60,23 +60,27 @@ state.
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## Link aggregation
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A LAG is a port to the protocol, the way the vendor firmware presents it as
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Trk1 to Trk4. The four groups are entities alongside the nine physical ports:
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they carry their own path cost, priority, edge and guard settings, they hold
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their own timers, and they appear as their own rows on the Spanning Tree page.
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A LAG (Link Aggregation Group) is handled like an additional port by the STP
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protocol, with its own timers and states. The switch devices support up to 4
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LAGs, which are shown alongside the physical ports in the STP status. A group
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carries its own path cost, priority, edge and guard settings, and gets its own
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row on the Spanning Tree page.
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```
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stp lag 1 cost 10000 # the group decides, not its members
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stp lag 1 edge off
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```
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Membership comes from the aggregation registers the `lag` command writes, re-read
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once a second, so a group changing under LACP is picked up without any
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coordination between the two. A member port is not an STP port of its own:
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`stp port <n>` on a member says which group to configure instead. State
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changes are written to every member in one register write, since the hardware
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has no per-group state, and BPDUs are transmitted through the lowest
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member while carrying the group's own port id. Losing one member of a live
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LAGs are configured via the `lag` command. Once a port is a member of a LAG it
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can no longer be configured individually for STP, so `stp port <n>` on a member
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tells you which group to configure instead. Membership is re-read from the
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aggregation registers once a second, so a group changing under LACP is picked
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up without any coordination between the two.
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The switch hardware does not handle STP state for a LAG as a whole. State
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changes for the members have to be done by the firmware, updating every member
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port, which is possible using a single register write. BPDUs go out through the
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lowest member and carry the group's own port id. Losing one member of a live
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LAG is not a topology change; the logical port only goes down with its last
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link.
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+15
-15
@@ -47,7 +47,7 @@ __xdata uint8_t stp_rstp; /* 1 = RST BPDUs, 0 = legacy Config BPDUs */
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__xdata uint8_t stp_txhold; /* BPDUs per port per second */
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__xdata uint8_t stp_ent_of[10];
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__xdata uint8_t stp_ent_of[STP_PORTS];
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__xdata uint16_t stp_lag_mask[STP_LAG_COUNT];
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__xdata uint8_t stp_ss_i;
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__xdata uint8_t stp_map_dirty;
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@@ -248,9 +248,9 @@ static void stp_status(void)
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stp_st_of = stp_i;
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if (stp_i >= STP_LAG_BASE) {
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stp_st_of = 0;
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while (stp_st_of < 10 && !((stp_lag_mask[stp_i - STP_LAG_BASE] >> stp_st_of) & 1))
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while (stp_st_of < STP_PORTS && !((stp_lag_mask[stp_i - STP_LAG_BASE] >> stp_st_of) & 1))
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stp_st_of++;
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if (stp_st_of >= 10)
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if (stp_st_of >= STP_PORTS)
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stp_st_of = 0;
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}
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print_field(stp_state_txt, (sfr_data[3 - (stp_st_of >> 2)] >> ((stp_st_of << 1) & 0x7)) & 0x3, 5);
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@@ -300,14 +300,14 @@ int8_t cmpBytes(__xdata uint8_t *m1, __xdata uint8_t *m2, uint8_t n) __reentrant
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static void stp_lag_map(void)
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{
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for (stp_ss_i = 0; stp_ss_i < 10; stp_ss_i++)
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for (stp_ss_i = 0; stp_ss_i < STP_PORTS; stp_ss_i++)
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stp_ent_of[stp_ss_i] = stp_ss_i;
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for (stp_scratch = 0; stp_scratch < STP_LAG_COUNT; stp_scratch++) {
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stp_scratch16 = port_lag_members_get(stp_scratch);
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if (stp_lag_mask[stp_scratch] != stp_scratch16)
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stp_map_dirty = 1;
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stp_lag_mask[stp_scratch] = stp_scratch16;
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for (stp_ss_i = 0; stp_ss_i < 10; stp_ss_i++)
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for (stp_ss_i = 0; stp_ss_i < STP_PORTS; stp_ss_i++)
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if ((stp_lag_mask[stp_scratch] >> stp_ss_i) & 1)
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stp_ent_of[stp_ss_i] = STP_LAG_BASE + stp_scratch;
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}
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@@ -336,7 +336,7 @@ static uint8_t stp_state_port(uint8_t e) __reentrant
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{
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if (e < STP_LAG_BASE)
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return e;
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for (stp_ss_i = 0; stp_ss_i < 10; stp_ss_i++)
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for (stp_ss_i = 0; stp_ss_i < STP_PORTS; stp_ss_i++)
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if ((stp_lag_mask[e - STP_LAG_BASE] >> stp_ss_i) & 1)
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return stp_ss_i;
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return 0;
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@@ -345,7 +345,7 @@ static uint8_t stp_state_port(uint8_t e) __reentrant
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static void stp_state_bits(uint8_t port, uint8_t state) __reentrant
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{
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for (stp_ss_i = 0; stp_ss_i < 10; stp_ss_i++)
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for (stp_ss_i = 0; stp_ss_i < STP_PORTS; stp_ss_i++)
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if (stp_ent_has(port, stp_ss_i))
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sfr_data[3 - (stp_ss_i >> 2)] |= (uint8_t)(state << ((stp_ss_i << 1) & 0x7));
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}
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@@ -355,7 +355,7 @@ static void stp_state_bits(uint8_t port, uint8_t state) __reentrant
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static void stp_state_set(uint8_t port, uint8_t state) __reentrant
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{
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reg_read_m(RTL837X_MSTP_STATES);
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for (stp_ss_i = 0; stp_ss_i < 10; stp_ss_i++) {
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for (stp_ss_i = 0; stp_ss_i < STP_PORTS; stp_ss_i++) {
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if (!stp_ent_has(port, stp_ss_i))
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continue;
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stp_scratch = 3 - (stp_ss_i >> 2);
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@@ -466,9 +466,9 @@ void stp_cnf_send(uint8_t port) __reentrant
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STP_O->rtl_tag.flags = HTONS(RTL_TAG_LEARN_DIS);
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if (port >= STP_LAG_BASE) {
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stp_scratch = 0;
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while (stp_scratch < 10 && !stp_ent_has(port, stp_scratch))
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while (stp_scratch < STP_PORTS && !stp_ent_has(port, stp_scratch))
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stp_scratch++;
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if (stp_scratch >= 10) {
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if (stp_scratch >= STP_PORTS) {
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stp_tx_flags_extra = 0;
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return;
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}
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@@ -739,9 +739,9 @@ void stp_timers(void) __banked
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}
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if (stp_link_now != stp_link_prev) {
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for (stp_i = 0; stp_i < STP_ENTITIES; stp_i++) {
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if (stp_i < 10 && (stp_i < machine.min_port || stp_i > machine.max_port))
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if (stp_i < STP_PORTS && (stp_i < machine.min_port || stp_i > machine.max_port))
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continue;
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if (stp_i < 10 && stp_ent_of[stp_i] != stp_i)
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if (stp_i < STP_PORTS && stp_ent_of[stp_i] != stp_i)
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continue;
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if (!(stp_pflags[stp_i] & STP_PF_ENABLED))
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continue;
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@@ -834,7 +834,7 @@ void stp_defaults(void) __banked
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stp_fwddelay_s = 15;
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stp_rstp = 1;
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stp_txhold = 6;
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for (stp_i = 0; stp_i < 10; stp_i++)
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for (stp_i = 0; stp_i < STP_PORTS; stp_i++)
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stp_ent_of[stp_i] = stp_i;
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for (stp_i = 0; stp_i < STP_LAG_COUNT; stp_i++)
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stp_lag_mask[stp_i] = 0;
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@@ -896,11 +896,11 @@ void stp_setup(void) __banked
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stp_tx_count[stp_i] = 0;
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port_timers[stp_i] = 0;
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port_hello[stp_i] = (uint16_t)stp_hello_s * STP_HZ;
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if (stp_i < 10 && (stp_i < machine.min_port || stp_i > machine.max_port))
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if (stp_i < STP_PORTS && (stp_i < machine.min_port || stp_i > machine.max_port))
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continue;
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if (stp_i >= STP_LAG_BASE && !stp_lag_mask[stp_i - STP_LAG_BASE])
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continue;
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if (stp_i < 10 && stp_ent_of[stp_i] != stp_i)
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if (stp_i < STP_PORTS && stp_ent_of[stp_i] != stp_i)
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continue;
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if (!(stp_pflags[stp_i] & STP_PF_ENABLED)
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|| (stp_pflags[stp_i] & STP_PF_ADMEDGE)) {
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+3
-1
@@ -2,6 +2,7 @@
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#define _RTL837X_STP_H_
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#include <stdint.h>
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#include "rtl837x_common.h"
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void stp_in(void) __banked;
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void stp_setup(void) __banked;
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void stp_timers(void) __banked;
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@@ -12,7 +13,8 @@ void stp_defaults(void) __banked;
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/* Tick rate of stp_timers(), also used by the web UI. */
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#define STP_HZ 50
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#define STP_LAG_BASE 10
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#define STP_PORTS (CPU_PORT + 1)
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#define STP_LAG_BASE STP_PORTS
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#define STP_LAG_COUNT 4
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#define STP_ENTITIES (STP_LAG_BASE + STP_LAG_COUNT)
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