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Update Readme
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logicog
@@ -1,56 +1,60 @@
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# RTLPlayground
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A Playground for Firmware development for RTL8372/RTL8373 based 2.5GBit Switches.
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A Playground for Firmware development for advanced user of RTL8372/RTL8373 based 2.5GBit Switches.
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For each hardware configuration of these devices, there is usually a managed and an
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umanaged version sold, with mostly identical hardware. The aim is to provide management
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features also for unmanaged devices with additional features such as Management VLAN,
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dhcp servers, multi-language support, IPv6 and TLS-encrypted web-pages.
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dhcp servers, multi-language support, IPv6 and TLS-encrypted web-pages. At present, however
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only the following features are provided:
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- A modern web-interface with mouse-over to display further information
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- A serial console interface to configure all features
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- IGMP to configure Multicast streaming
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- Port configuration showing detailed informtion about own and Link-partner advertised
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Speed settins and configuration of these settings on the local side
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- Per-port configuration of frame sizes (MTUs) for Jumbo-Frame support or limiting MTUs
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for particular devices
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- EEE (Energy Efficient Ethernet) can be configured per-port. Detailed information is
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provided for support offered by the link partner and the EEE status of a port.
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- VLAN configuration
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- SFP information is displayed on the inserted modules, the current sensor values such as
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temperatures, RX and TX power are displayed in the CLI and as mouse-over on the web
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- Mirror configuration
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- Link Aggregation Groups can be set up
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- Detailed information on port packet statistics
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- Configuration saved to flash via the web-interface
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- Firmware updates via the web
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- Installation as a firmware upgrade from the original web-interface
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The playground currently provides a minimal alternative firmware for both the managed and unmanaged switches.
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When used with unmanaged switches, it will provide some management features such as
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setting up VLANs, mirroring ports and provide a Web-Server (currently no functions,
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really), but will need to be configured via a serial connection. Installation on
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managed devices only makes sense for developers, as plenty of features of the managed
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switches are not supported, yet.
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<img width="1420" height="623" alt="GUI" src="doc/images/gui.png" />
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At this point, the firmware can be installed on the hardware as given below,
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all of the ports and SFP-slots will be supported. The following has been tested:
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On the keepLINK kp-9000-6hx-x (RTL8372 + RTL8221B 2.5GBit PHY: 5 x 2.5GBit + 1x 10GBit SFP+),
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at present the system will provide the same featurs as a dumb switch plus a tiny
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TCP stack that will allow to reply to ARP and ping messages, thus enabling pinging the device.
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VLAN and mirroring can be configured (but not saved to flash).
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The ports served by the RTL8372 will be 100M/1G/2.5G auto-detect. Port 5 to RTL8221B PHY
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SerDes configuration works and supports 1GBit and 2.5GBit Ethernet (SGMII/HISGMII).
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SFP module insert/removal identification and reading of the SFP EEProm works. SFP
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module configuration works, too, tested for 1G, 2.5G and 10G Ethernet and Fiber modules.
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While the firmware provides already considerable improvements over the original managed firmware,
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the firmware still lacks support for STP and the proprietary loop prevention
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protocols as well as DHCP. If you need these features, do not install the playground on your managed
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devices. In any case, installation is strongly discouraged unless you can at least make
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a backup of the original flash content via a SOIC clamp such as also used for BIOS
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backups and can re-install that firmware in case something is wrong. For this no soldering
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skills are necessary.
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The 4-Port Ethernet + 2 Port SFP+ devices (e.g. KP-9000-6HX-x2) are fully supported, too
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(e.g. KP-9000-6hx-x2) with the same features as above. In particular all fiber/Ethernet
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modules work in both SFP+ ports.
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On the 9-port devices with RTL8273 + RTL8224 (for example kp-9000-9xh-x) all ports will
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work for switching and CPU-access, the SFP+ port will work normally and TCP connectivity
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will work as above. Not all features of the RTL8224-ports (the first 4) have been tested.
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The firmware supports all hardware featues of devices with
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- 4 2.5GBit ports + 2 SFP+ ports
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- 5 2.5GBIT + 1 SFP+ port
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- 8 2.5GBit + 1 SFP+ port
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Devices sold usually have a fairly common design, however there may be differences in the LED
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configuration (switches have LEDs with different colours and use types of LEDs). The list
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of tested devices can be found in [Supported devices](doc/supported_devices.md).
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To do meaningful development you will need to use a serial console, so soldering skills
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are required. Flashing must be done via a SOIC-8 PatchClamp or by soldering a socket
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for the flash chip.
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UPDATE: The Code comes with a port of the [uIP](https://github.com/adamdunkels/uip)
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TCP/IP stack and includes a minimal web-server that can be used to work with the switch,
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so if you use a patch-clamp for updating the firmware (~3 USD/EUR), you can try this
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out without the need to solder anything. See the instructions below.
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Note that updating the firmware of a managed switch with the images created in this
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project via the OEM web-interface will not work, because it is currently unknown how
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to generate the require checksum, see this
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[issue](https://github.com/up-n-atom/SWTG118AS/issues/4).
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However, if you use the patch-clamp to flash, this is not a problem.
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If you don't want to open your device, you can use the project's code to learn about the
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devices by looking at the image using e.g. Ghidra.
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devices by looking at the image using e.g. Ghidra. If you want to contribute to the
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design of the web-interface or get a feeling for the interface first, a standalone
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device simulator is provided, which runs entirely under Linux as a local webserver.
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## Compiling
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Install the following particular build requisites (Debian 12, should work on Ubuntu)
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Install the following particular build requisites (Debian 12/13), note that Ubuntu 24.04
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still has an older version of sdcc, but you will need sdcc version 4.5 for the code to compile:
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```
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sudo apt install sdcc xxd python-is-python3 libjson-c-dev
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```
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@@ -70,126 +74,35 @@ cat rtlplayground.img >> rtlplayground.bin
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Note, that the image generated ends in .bin, not .img, in order to make
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IMSProg happy.
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Managed switches can be updated from the existing original firmware using an upgrade image.
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In the `installer`folder of the source code you will need to run `make` which will build
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an image out of `rtlplayground.bin` built in the previous step:
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```
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RTLPlayground/installer$ make
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mkdir -p output/
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gcc updatebuilder.c -o output/updatebuilder
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sdas8051 -plosgff -o output/crtstart.rel crtstart.asm
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sdcc -mmcs51 --code-loc 0x1000 -o output/installer.rel -c installer.c
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sdcc -mmcs51 -Wl-bHOME=0x1100 -Wl-r -o output/rtlinstaller.ihx output/crtstart.rel output/installer.rel
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cp ../output//rtlplayground.bin output/
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./output//updatebuilder -i output/rtlinstaller.ihx output/rtlplayground.bin
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Input file size: 524288
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Bytes read: 524288
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EOF
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Payload sum 1 is: 0x29d10
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Payload sum 2 is: 0x29d10
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Payload sum with header is: 0x2b0fc
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Payload sum is: 0xad8a75
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Header checksum is: 0x4c3
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```
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The resulting image can be found in `RTLPlayground/installer/output/rtlplayground.bin`
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> [!CAUTION]
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> DO NOT UPLOAD THE UPGADE IMAGE UNLESS YOU CAN MAKE A BACKUP USING A SOIC CLAMP OF THE
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> ORIGINAL FIRMWARE!
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## Installation
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You can play with the image using ghidra or flash real Switch Hardware
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### Supported Hardware
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If you do not have an RTL837x-based switch device such as the ones
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mentionned here: [Up-N-Atoms 2.5 GBit RTL Switch hacking guide]
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(https://github.com/up-n-atom/SWTG118AS) or one of the other that
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deployment was tested on, including:
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- keepLINK kp-9000-6hx-x2 (RTL8372: 4x 2.5GBit + 2x 10GBit SFP+)
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- keepLINK KP-9000-6XHML-X2, same as above, but Managed
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- keepLINK kp-9000-6hx-x (RTL8372 + RTL8221B 2.5GBit PHY: 5 x 2.5GBit + 1x 10GBit SFP+)
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- keepLINK kp-9000-9xh-x-eu (1 x RTL8373 + RTL8224: 8x 2.5GBit + 1x 10GBit SFP+)
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- Lianguo LG-SWTGW218AS (RTL8373 + RTL8224 PHY: 8x 2.5GBit + 1x 10GBit SFP+)
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- No-Name ZX-SWTGW215AS, managed version of kp-9000-6hx-x, ordered on
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AliExpress as keepLINK 5+1 port managed
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### Understanding the image using ghidra
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Start ghidra, load file starting from offset 0x0002 into
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memory starting at 0x0000. The lengthe is 0x10000. Select generic 8051, big
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endian.
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After loading, the boot vector is at 0x0000, which will jump to 0x0100 for
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the boot routine.
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The firmware uses only bank 1 of the RTL837x since it is quite short.
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Otherwise the firmware would be organized as follows
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```
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--------------------------- 0x0000 ---------------------------------
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Boot-Vector
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ISRs
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Common Code
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Trampoline for inter-bank calls
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Inter-bank calls, calling trampoline, one for each callable function
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----- Bank 1 0x4000 ------ ---- Bank 2 0x4000 ----- -------- .....
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Overlay 1 Overlay 2 Overlay n
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--------- 0xffff --------- -------- 0xffff -------- -------- 0xffff
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```
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The RTL837x firmware images are organized as follows:
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The first 2 bytes of the image give the size of the prefetched data at the
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start of the CPU power up. The default is 0x4000 (bytes: 0x00 0x40), which
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means that the entire shared area of the code memory in all banks,
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0x4000 bytes is read immediately into the code RAM.
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Common code starts at
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0x0002 in the image and has length 0x3ffd, the first bank starts at 0x4000
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in the image, is mapped to 0x4000 and has length 0xc000. The second bank
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starts at 0x10000, is mapped to 0x4000 and has length 0xc000. The third
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bank would start at 0x1c000 and would again be mapped to 0x4000.
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There are about 30 banks in use for managed switches, unmanaged ones use
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2-3, while the hardware would allow to use 0x3f banks, i.e. up to 4 MB of
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flash.
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The current image uses Common BANK0 and the first BANK1 via sdccs __banked
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function keyword and custom banking trampoline code for the RTL837x in
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assembler.
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### Hardware supported by the code so far
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-The following hardware is supported:
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- Clock generation, including different divider settings
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- Interrupt control for timer, serial, external irqs 0, 1
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- Serial console via SFRs
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- Flash operations via SFRs
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- Bank switching via SFRs
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- Access to Switch registers via SFRs
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- LED setup
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- Reset
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- Some switch settings such as MAC configuration
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- GPIO to detect SFP module insert/removal/RX-LOS
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- I2C to read SFP EEPROM on 1 and 2 SFP slot devices
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- NIC setup
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- L2 learning table access, L2 table flushing
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- VLAN setup/configuration
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- Port mirroring
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- Access to PHYs via MDIO (clause 45 via SFR):
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- Internal PHYs of RTL8372 and RTL8373
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- RTL8221 (1x2.5GBit port on devices with 5 ports)
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- RTL8224 (4x2.5GBit ports on devices with 8 ports)
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- SerDes settings of SoC via SFR:
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- Configure SFPs with 10Gbit/2.5Gbit/1Gbit (Ethernet and Fiber SFP(+) tested)
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- RTL8221, RTL8224
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- NIC TX and RX of packets via SFRs
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- send and receive Ethernet frames via SFRs and Switch registers
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- RTL-tags and VLAN ingress-tag decoding for CPU-port
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Ethernet frame RX IRQ via IRQ1 is conceptually understood, but not activated. RX is
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currently done via polling, which allows ping-times of <10ms.
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||||
|
||||
The RTL8372/3 have 256 bytes of internal RAM (INTMEM) accessible through MOV
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instructions, which are used for the stack and important globals. Some of
|
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these are bit-adressable, e.g. for storing global flags.
|
||||
|
||||
Additionally, 64kB of extended RAM (XMEM) is built in, which is accessed
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through the MOVX instruction. It is used for global variables, for most
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of the function argument passing that is not done using the 8 registers
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R0-R7 or registers A/B, and for local variables (which requires extremely
|
||||
careful planning). The flash memory is transparently accessible for code
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being executed and can be used to store configuration. Access is done through
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the MOVC instruction, possibly setting the bank register before and
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resetting it to access the entire 4MB space. Code is prefetched from flash
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and cached in a small RAM automatically by the HW.
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The peripherial functions are accessed through 2 different mechanisms:
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- Special Function Registers (SFRs, 0x80-0xff) for banking, timers, UART, access to
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switch registers, MDIO, SPI (flash) and NIC transfers. Some SFRs are not
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used for HW purposes and can be used as RAM. Some SFRs are bit-adressable,
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allowing for very tight event wait loops (a single 2-byte instruction).
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- 0x10000 switch registers, which appear to be very similar to the registers
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||||
of the RTL838x, for which source code and datasheets are available. This
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controls clock dividers, GPIO/LEDs and general switch functionality.
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||||
|
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The playground image shows access to the different types of memory using the
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SDCC compiler. Any support of Linux or e.g. Zephyr would require porting gcc.
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||||
There are FreeRTOS ports to 8051 processors using sdcc, however.
|
||||
|
||||
|
||||
### Installation on an actual switch
|
||||
You can play with the image using ghidra or flash real Switch Hardware. For
|
||||
ghidra see this information about [Ghidra images](ghidra.md).
|
||||
|
||||
> [!CAUTION]
|
||||
> NOTE THAT WHILE THIS PROCEDURE HAS BEEN SUCCESSFULLY TESTED ON ALL DEVICES ABOVE,
|
||||
@@ -197,8 +110,15 @@ There are FreeRTOS ports to 8051 processors using sdcc, however.
|
||||
> ANY OTHER EQUIPMENT INVOLVED OR HARM YOURSELF BY OPENING THE ELECTRONIC
|
||||
> DEVICE. OPENING THE SWITCH WILL VOID ITS WARRANTY.
|
||||
|
||||
There is no support for uploading the firmware via ethernet. Instead you
|
||||
need to open the switch and flash the image directly onto the flash chip,
|
||||
You can upload the upgrade image of managed switches via the web interface of the
|
||||
original firmware just as if you were installing a firmware upgrade. However,
|
||||
this is strongly discouraged, as you may brick your device, unless you can make
|
||||
firmware backups via a SOIC clamp or soldered flash socket, first!
|
||||
|
||||
For unmanaged devices, the only way to install RTLPlayground is by flashing the
|
||||
Flash memory directly.
|
||||
|
||||
You will need to open your switch to flash the image directly onto the flash chip,
|
||||
which is done easiest using a SOIC-8 clip (alternatively you de-solder the
|
||||
flash chip and install a SOIC adapter):
|
||||
- Disconnect power from switch
|
||||
@@ -217,6 +137,10 @@ devices, set 8N1 @ 115200 baud and power up the switch.
|
||||
The device will perform some examples and provide a minimal console, the
|
||||
documentation of which can be found in the source code rtlplayground.c`.
|
||||
|
||||
## The web-interface
|
||||
The web-interface can be reached under the [default 192.168.10.247](http://192.168.10.247).
|
||||
The default password is `1234`.
|
||||
|
||||
## The command line
|
||||
The command line is very rudimentary and mostly for testing purposes.
|
||||
The following is a boot-log with some examples:
|
||||
@@ -307,6 +231,7 @@ Enjoy playing!
|
||||
## Other documents
|
||||
The following documents give further documentation on specific features of
|
||||
the RTL837x SoCs:
|
||||
- [RTL8372/3 Feature support](doc/hardware.md)
|
||||
- [CPU Port](doc/CpuPort.md)
|
||||
- [L2 learning](doc/l2.md)
|
||||
- [CPU Port](doc/CpuPort.md)
|
||||
|
||||
@@ -0,0 +1,41 @@
|
||||
# Understanding the image using ghidra
|
||||
Start ghidra, load file starting from offset 0x0002 into
|
||||
memory starting at 0x0000. The lengthe is 0x10000. Select generic 8051, big
|
||||
endian.
|
||||
|
||||
After loading, the boot vector is at 0x0000, which will jump to 0x0100 for
|
||||
the boot routine.
|
||||
|
||||
The firmware uses only bank 1 of the RTL837x since it is quite short.
|
||||
Otherwise the firmware would be organized as follows
|
||||
```
|
||||
--------------------------- 0x0000 ---------------------------------
|
||||
Boot-Vector
|
||||
ISRs
|
||||
Common Code
|
||||
Trampoline for inter-bank calls
|
||||
Inter-bank calls, calling trampoline, one for each callable function
|
||||
|
||||
----- Bank 1 0x4000 ------ ---- Bank 2 0x4000 ----- -------- .....
|
||||
Overlay 1 Overlay 2 Overlay n
|
||||
|
||||
--------- 0xffff --------- -------- 0xffff -------- -------- 0xffff
|
||||
```
|
||||
The RTL837x firmware images are organized as follows:
|
||||
The first 2 bytes of the image give the size of the prefetched data at the
|
||||
start of the CPU power up. The default is 0x4000 (bytes: 0x00 0x40), which
|
||||
means that the entire shared area of the code memory in all banks,
|
||||
0x4000 bytes is read immediately into the code RAM.
|
||||
|
||||
Common code starts at
|
||||
0x0002 in the image and has length 0x3ffd, the first bank starts at 0x4000
|
||||
in the image, is mapped to 0x4000 and has length 0xc000. The second bank
|
||||
starts at 0x10000, is mapped to 0x4000 and has length 0xc000. The third
|
||||
bank would start at 0x1c000 and would again be mapped to 0x4000.
|
||||
There are about 30 banks in use for managed switches, unmanaged ones use
|
||||
2-3, while the hardware would allow to use 0x3f banks, i.e. up to 4 MB of
|
||||
flash.
|
||||
|
||||
The current image uses Common BANK0 and the first BANK1 via sdccs __banked
|
||||
function keyword and custom banking trampoline code for the RTL837x in
|
||||
assembler.
|
||||
@@ -0,0 +1,58 @@
|
||||
#RTL8272/3 features
|
||||
|
||||
The following hardware features of the RTL8372/3 is supported:
|
||||
- Clock generation, including different divider settings
|
||||
- Interrupt control for timer, serial, external irqs 0, 1
|
||||
- Serial console via SFRs
|
||||
- Flash operations via SFRs
|
||||
- Bank switching via SFRs
|
||||
- Access to Switch registers via SFRs
|
||||
- LED setup
|
||||
- Reset
|
||||
- Some switch settings such as MAC configuration
|
||||
- GPIO to detect SFP module insert/removal/RX-LOS (depending on device/module support)
|
||||
- I2C to read SFP EEPROM on 1 and 2 SFP slot devices
|
||||
- NIC setup
|
||||
- L2 learning table access, L2 table flushing
|
||||
- VLAN setup/configuration
|
||||
- Port mirroring
|
||||
- Access to PHYs via MDIO (clause 45 via SFR):
|
||||
- Internal PHYs of RTL8372 and RTL8373
|
||||
- RTL8221 (1x2.5GBit port on devices with 5 ports)
|
||||
- RTL8224 (4x2.5GBit ports on devices with 8 ports)
|
||||
- SerDes settings of SoC via SFR:
|
||||
- Configure SFPs with 10Gbit/2.5Gbit/1Gbit (Ethernet and Fiber SFP(+) tested)
|
||||
- RTL8221, RTL8224
|
||||
- NIC TX and RX of packets via SFRs
|
||||
- send and receive Ethernet frames via SFRs and Switch registers
|
||||
- RTL-tags and VLAN ingress-tag decoding for CPU-port
|
||||
|
||||
Ethernet frame RX IRQ via IRQ1 is conceptually understood, but not activated. RX is
|
||||
currently done via polling, which allows ping-times of <10ms.
|
||||
|
||||
The RTL8372/3 have 256 bytes of internal RAM (INTMEM) accessible through MOV
|
||||
instructions, which are used for the stack and important globals. Some of
|
||||
these are bit-adressable, e.g. for storing global flags.
|
||||
|
||||
Additionally, 64kB of extended RAM (XMEM) is built in, which is accessed
|
||||
through the MOVX instruction. It is used for global variables, for most
|
||||
of the function argument passing that is not done using the 8 registers
|
||||
R0-R7 or registers A/B, and for local variables (which requires extremely
|
||||
careful planning). The flash memory is transparently accessible for code
|
||||
being executed and can be used to store configuration. Access is done through
|
||||
the MOVC instruction, possibly setting the bank register before and
|
||||
resetting it to access the entire 4MB space. Code is prefetched from flash
|
||||
and cached in a small RAM automatically by the HW.
|
||||
|
||||
The peripherial functions are accessed through 2 different mechanisms:
|
||||
- Special Function Registers (SFRs, 0x80-0xff) for banking, timers, UART, access to
|
||||
switch registers, MDIO, SPI (flash) and NIC transfers. Some SFRs are not
|
||||
used for HW purposes and can be used as RAM. Some SFRs are bit-adressable,
|
||||
allowing for very tight event wait loops (a single 2-byte instruction).
|
||||
- 0x10000 switch registers, which appear to be very similar to the registers
|
||||
of the RTL838x, for which source code and datasheets are available. This
|
||||
controls clock dividers, GPIO/LEDs and general switch functionality.
|
||||
|
||||
The playground image shows access to the different types of memory using the
|
||||
SDCC compiler. Any support of Linux or e.g. Zephyr would require porting gcc.
|
||||
There are FreeRTOS ports to 8051 processors using sdcc, however.
|
||||
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|
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|
||||
# Supported Hardware
|
||||
The following devices have been tested and are fully working:
|
||||
- Horaco ZX_SG4T2
|
||||
- keepLINK kp-9000-6hx-x2 (RTL8372: 4x 2.5GBit + 2x 10GBit SFP+)
|
||||
- keepLINK KP-9000-6XHML-X2, same as above, but Managed
|
||||
- keepLINK kp-9000-6hx-x (RTL8372 + RTL8221B 2.5GBit PHY: 5 x 2.5GBit + 1x 10GBit SFP+)
|
||||
- keepLINK kp-9000-9xh-x-eu (1 x RTL8373 + RTL8224: 8x 2.5GBit + 1x 10GBit SFP+)
|
||||
- Lianguo LG-SWTGW218AS (RTL8373 + RTL8224 PHY: 8x 2.5GBit + 1x 10GBit SFP+)
|
||||
- No-Name ZX-SWTGW215AS, managed version of kp-9000-6hx-x, ordered on
|
||||
AliExpress as keepLINK 5+1 port managed
|
||||
|
||||
Other device based on RTL8272/3 that may work are described here: [Up-N-Atoms 2.5 GBit RTL Switch hacking guide]
|
||||
(https://github.com/up-n-atom/SWTG118AS)
|
||||
|
||||
Many of the RTL8272/3 devices come in versions with PoE support. The RTLPlayground usually also
|
||||
works on these, however, no support for configuring PoE is provided, simply because these
|
||||
devices usually just provide PoE on all ports without further configuration possibilitites.
|
||||
|
||||
The following forum also discusses this type of switches: [ServeTheHome](https://forums.servethehome.com/index.php?threads/horaco-2-5gbe-managed-switch-8-x-2-5gbe-1-10gb-sfp.41571/)
|
||||
|
||||
There are also 16-port unmanaged devices with RTL8272 SoCs, however these devices do not have
|
||||
serial consoles and use 4 independent RTL8272 SoCs. No central control is provided by RTLPlayground,
|
||||
even if it has been successfully demonstrated to install RTLPlayground to individual SoCs.
|
||||
- [GigaPlus GP-S25-1602](https://www.servethehome.com/gigaplus-gp-s25-1602-review-a-cheap-16-port-2-5gbe-and-2-port-10g-switch/)
|
||||
- [Vimin VM S251602P 16 Port 2.5G PoE Switch With 2x 10G SFP+](https://www.servethehome.com/vimin-vm-s251602p-16-port-2-5g-poe-switch-review-cyperf/vimin-vm-s251602p-16-port-2-5g-poe-switch-with-2x-10g-sfp-battery-2/)
|
||||
Reference in New Issue
Block a user