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Demagic PHY_MMD31, 0xa400 to PHY_MMD31, PHY_MMD31_FEDCR
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@@ -34,6 +34,7 @@
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/*
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* MMD 31 Registers
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*/
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#define PHY_MMD31_FEDCR 0xa400
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#define PHY_MMD31_GBCR 0xa412
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+5
-5
@@ -132,10 +132,10 @@ void phy_config(uint8_t phy) __banked
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// p031f.a400:1040 P000008.1f00a400:5040, then: p031f.a400:5040 P000008.1f00a400:1040
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// FEDCR (Fast Ethernet Duplex Control Register, MMD 31.0xA400)
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// Set bit 14, sleep, then clear again, according to the datasheet these bits are reserved
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phy_modify(phy, PHY_MMD31, 0xa400, 0x0000, 0x4000);
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phy_modify(phy, PHY_MMD31, PHY_MMD31_FEDCR, 0x0000, 0x4000);
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delay(20);
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phy_modify(phy, PHY_MMD31, 0xa400, 0x4000, 0x0000);
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phy_modify(phy, PHY_MMD31, PHY_MMD31_FEDCR, 0x4000, 0x0000);
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delay(20);
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print_string("\r\n phy config done\r\n");
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@@ -259,13 +259,13 @@ void phy_set_duplex(uint8_t port, uint8_t fullduplex) __banked
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phy_read(port, PHY_MMD_AN, 0x00);
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v = SFR_DATA_U16;
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if (!(v & 0x1000)) { // AN disabled, we are in forced mode
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phy_read(port, PHY_MMD31, 0xa400);
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phy_read(port, PHY_MMD31, PHY_MMD31_FEDCR);
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v = SFR_DATA_U16;
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if (fullduplex)
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v |= 0x0100;
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else
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v &= 0xfeff;
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phy_write(port, PHY_MMD31, 0xa400, v);
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phy_write(port, PHY_MMD31, PHY_MMD31_FEDCR, v);
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return;
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}
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// Disable AN
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@@ -363,7 +363,7 @@ void phy_show(uint8_t port) __banked
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default:
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print_string("Unknown\n");
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}
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phy_read(port, PHY_MMD31, 0xa400);
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phy_read(port, PHY_MMD31, PHY_MMD31_FEDCR);
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v = SFR_DATA_U16;
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print_string("Duplex: "); print_short(v); print_string(" enabled: ");
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if (v & 0x100)
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