From d8658626252daaae3322d3c65af79ea4f45df07b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= Date: Sun, 31 Aug 2025 22:18:30 +0200 Subject: [PATCH] phy: fix or/and-opperation conversion errors --- rtl837x_phy.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rtl837x_phy.c b/rtl837x_phy.c index fbceb67..218a74b 100644 --- a/rtl837x_phy.c +++ b/rtl837x_phy.c @@ -116,7 +116,7 @@ void phy_config(uint8_t phy) __banked // p031f.a432:0811 P000008.1f00a432:0831 // PHYCR2 PHY Specific Control Register 2, MMD 31. 0xA432), set bit 5: enable EEE phy_read(phy, 0x1f, 0xa432); - pval = SFR_DATA_U16 | 0x0021; + pval = SFR_DATA_U16 | 0x0020; phy_write(phy, 0x1f, 0xa432, pval); // p0307.003e:0000 P000008.0700003e:0001 @@ -129,7 +129,7 @@ void phy_config(uint8_t phy) __banked // p031f.a442:043c P000008.1f00a442:0430 // Unknown, but clear bits 2/3 phy_read(phy, 0x1f, 0xa442); - pval = SFR_DATA_U16 & 0x00f3; + pval = SFR_DATA_U16 & 0xfff3; phy_write(phy, 0x1f, 0xa442, pval); delay(20); @@ -147,7 +147,7 @@ void phy_config(uint8_t phy) __banked // p081f.d040:ffff P000100.1f00d040:feff // LCR6 (LED Control Register 6, MMD 31.D040), set bits 8/9 to 0b10 phy_read(phy, 0x1e, 0xd040); - pval = SFR_DATA_U16 & 0xfc00 | 0x0002; + pval = SFR_DATA_U16 & 0xfcff | 0x0200; phy_write(phy, 0x1e, 0xd040, pval); delay(20);