From d79ac79f2ffaab6c703a39767189fa68a2880aa7 Mon Sep 17 00:00:00 2001
From: air jinkela <air_jinkela@163.com>
Date: Mon, 11 Aug 2025 08:49:56 +0800
Subject: [PATCH] update doc/l2.md

---
 doc/l2.md | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/doc/l2.md b/doc/l2.md
index cd7003f..c0aaf61 100644
--- a/doc/l2.md
+++ b/doc/l2.md
@@ -32,7 +32,7 @@ cleared by the ASIC. Data then is in the output data registers
 #define RTL837x_L2_DATA_OUT_C	0x5cd4
 
 DATA_OUT_A   DATA_OUT_B   L2_DATA_OUT_C
-M2 M3 M4 M5  fV VV M0 M1  xx xF xx xg
+M2 M3 M4 M5  fV VV M0 M1  xx xF xx gg
 
 M0-M5: 6 bytes of MAC, M0 is MSB
 V: 12 bits of VLAN-ID
@@ -41,6 +41,9 @@ f: bit 5 set: Entry is valid, otherwise stale
    bit 7: bit 1 of port-number
 g: bit 0: bit 2 of port-number
    bit 1: bit 3 of port-number (MSB)
+   bit 2: bit 0 of entry-age
+   bit 3: bit 1 of entry-age
+   bit 4: bit 2 of entry-age (MSB)
 F: bit 0: entry is static(1) or learned (0)
 ```
 The next entry can be now found in RTL837x_TBL_DATA_0 (entry = RTL837x_TBL_DATA_0_bits(0-11) + 1),