mirror of
https://github.com/logicog/RTLPlayground.git
synced 2026-08-30 14:52:51 +08:00
Use machine structure
This commit is contained in:
logicog
+42
-51
@@ -15,6 +15,9 @@
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#include "uip/uipopt.h"
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#include "uip/uip.h"
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#include "uip/uip_arp.h"
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#include "machine.h"
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extern __code struct machine machine;
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extern __xdata uint16_t crc_value;
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__xdata uint8_t crc_testbytes[10];
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@@ -56,8 +59,6 @@ __code struct uip_eth_addr uip_ethaddr = {{ 0x1c, 0x2a, 0xa3, 0x23, 0x00, 0x02 }
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__code uint8_t gatewayIP[] = { 192, 168, 2, 22};
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__code uint8_t netmask[] = { 255, 255, 255, 0};
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__xdata uint8_t isRTL8373;
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volatile __xdata uint32_t ticks;
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volatile __xdata uint8_t sec_counter;
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volatile __xdata uint16_t sleep_ticks;
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@@ -87,10 +88,6 @@ __xdata uint8_t uip_buf[UIP_CONF_BUFFER_SIZE+2];
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__xdata uint16_t rx_packet_vlan;
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__xdata uint8_t tx_seq;
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__xdata uint8_t minPort;
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__xdata uint8_t maxPort;
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__xdata uint8_t nSFPPorts;
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__xdata uint8_t cpuPort;
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__xdata uint8_t stpEnabled;
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__code uint16_t bit_mask[16] = {
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@@ -633,7 +630,7 @@ void sds_config_mac(uint8_t sds, uint8_t mode)
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case 2:
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sfr_mask_data(1, 0xfc, 0x02 << 2);
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}
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if (isRTL8373) // Set 3rd SERDES Mode to 0x2 for RTL8224
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if (machine.isRTL8373) // Set 3rd SERDES Mode to 0x2 for RTL8224
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sfr_mask_data(1, 0xfc, 0x02 << 2);
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else
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sfr_data[2] &= 0x03;
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@@ -950,36 +947,36 @@ void handle_sfp(void)
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sfp_pins_last |= 0x02;
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print_string("\n<SFP-RX LOS>\n");
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}
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#if NSFP == 2
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reg_read_m(RTL837X_REG_GPIO_32_63_INPUT);
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if ((sfp_pins_last & 0x10) && (!(sfr_data[1] & 0x04))) {
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sfp_pins_last &= ~0x10;
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print_string("\n<MODULE 2 INSERTED> ");
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// Read Reg 11: Encoding, see SFF-8472 and SFF-8024
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// Read Reg 12: Signalling rate (including overhead) in 100Mbit: 0xd: 1Gbit, 0x67:10Gbit
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delay(100); // Delay, because some modules need time to wake up
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uint8_t rate = sfp_read_reg(1, 12);
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print_string("Rate: "); print_byte(rate); // Normally 1, but 0 for DAC, can be ignored?
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print_string(" Encoding: "); print_byte(sfp_read_reg(1, 11));
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print_string("\n");
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sfp_print_info(1);
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sds_config(0, sfp_rate_to_sds_config(rate));
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}
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if ((!(sfp_pins_last & 0x10)) && (sfr_data[1] & 0x04)) {
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sfp_pins_last |= 0x10;
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print_string("\n<MODULE 2 REMOVED>\n");
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}
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if (machine.n_sfp == 2) {
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reg_read_m(RTL837X_REG_GPIO_32_63_INPUT);
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if ((sfp_pins_last & 0x10) && (!(sfr_data[1] & 0x04))) {
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sfp_pins_last &= ~0x10;
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print_string("\n<MODULE 2 INSERTED> ");
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// Read Reg 11: Encoding, see SFF-8472 and SFF-8024
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// Read Reg 12: Signalling rate (including overhead) in 100Mbit: 0xd: 1Gbit, 0x67:10Gbit
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delay(100); // Delay, because some modules need time to wake up
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uint8_t rate = sfp_read_reg(1, 12);
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print_string("Rate: "); print_byte(rate); // Normally 1, but 0 for DAC, can be ignored?
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print_string(" Encoding: "); print_byte(sfp_read_reg(1, 11));
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print_string("\n");
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sfp_print_info(1);
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sds_config(0, sfp_rate_to_sds_config(rate));
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}
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if ((!(sfp_pins_last & 0x10)) && (sfr_data[1] & 0x04)) {
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sfp_pins_last |= 0x10;
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print_string("\n<MODULE 2 REMOVED>\n");
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}
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reg_read_m(RTL837X_REG_GPIO_00_31_INPUT);
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if ((sfp_pins_last & 0x20) && (!(sfr_data[2] & 0x08))) {
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sfp_pins_last &= ~0x20;
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print_string("\n<SFP2-RX OK>\n");
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reg_read_m(RTL837X_REG_GPIO_00_31_INPUT);
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if ((sfp_pins_last & 0x20) && (!(sfr_data[2] & 0x08))) {
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sfp_pins_last &= ~0x20;
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print_string("\n<SFP2-RX OK>\n");
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}
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if ((!(sfp_pins_last & 0x20)) && (sfr_data[2] & 0x08)) {
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sfp_pins_last |= 0x20;
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print_string("\n<SFP2-RX LOS>\n");
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}
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}
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if ((!(sfp_pins_last & 0x20)) && (sfr_data[2] & 0x08)) {
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sfp_pins_last |= 0x20;
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print_string("\n<SFP2-RX LOS>\n");
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}
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#endif
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}
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@@ -1035,7 +1032,7 @@ void idle(void)
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print_byte(linkbits_last[2]); print_byte(linkbits_last[3]);
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print_string(">\n");
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linkbits_last_p89 = linkbits_p89;
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if (!isRTL8373 && nSFPPorts != 2) {
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if (!machine.isRTL8373 && machine.n_sfp != 2) {
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uint8_t p5 = sfr_data[2] >> 4;
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uint8_t p5_last = linkbits_last[2] >> 4;
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cpy_4(linkbits_last, sfr_data);
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@@ -1420,7 +1417,7 @@ void led_config(void)
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reg_bit_clear(0x65dc, 0x1b);
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// Set bits 1b/1d of 0x7f8c: r7f8c:30000000 R7f8c-30000000 r7f8c:30000000 R7f8c-38000000
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if (nSFPPorts == 2) {
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if (machine.n_sfp == 2) {
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reg_bit_set(RTL837X_PIN_MUX_0, 0x1b); // R7f8c-28000000
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reg_bit_clear(RTL837X_PIN_MUX_0, 0x1c); // R7f8c-28000000
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reg_bit_set(RTL837X_PIN_MUX_0, 0x1d); // R7f8c-28000000
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@@ -1481,10 +1478,6 @@ void rtl8373_revision(void)
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void rtl8373_init(void)
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{
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print_string("\nrtl8373_init called\n");
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minPort = 0;
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maxPort = 8;
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cpuPort = 9;
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nSFPPorts = 1;
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// r6330:00015555 R6330-00005555 r6330:00005555 R6330-00005555
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REG_SET(0x6330, 0x00005555);
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@@ -1584,21 +1577,17 @@ void rtl8373_init(void)
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void rtl8372_init(void)
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{
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print_string("\nrtl8372_init called\n");
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minPort = 3;
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maxPort = 8;
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cpuPort = 9;
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nSFPPorts = NSFP;
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// r6330:00015555 R6330-00005555 r6330:00005555 R6330-00005555
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REG_SET(0x6330, 0x00005555);
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if (nSFPPorts == 2) {
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if (machine.n_sfp == 2) {
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print_string("Configuring 2nd SFP+ port\n");
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REG_SET(0x6330, 0x00005515);
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}
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// r6334:00000000 R6334-000001f8 RTL8373: r6334:00000000 R6334-000000ff
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reg_read_m(0x6334); // Also in sdsMode_set
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if (nSFPPorts == 2) {
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if (machine.n_sfp == 2) {
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sfr_mask_data(0, 0, 0xf0);
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} else {
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sfr_mask_data(1, 0, 0x01); // Set bits 3-8, On RTL8373+8224 set bits 0-7
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@@ -1643,7 +1632,7 @@ void rtl8372_init(void)
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// [...]
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///
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uint16_t reg = 0x1238 + 0x300; // Port base register for the bits we set
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for (char i = minPort; i <= maxPort; i++) {
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for (char i = machine.min_port; i <= machine.max_port; i++) {
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// Bit 7 (0x40) enables replacement of the RTL-VLAN tag with an 802.1Q VLAN tag
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REG_SET(reg, 0xe77);
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reg += 0x100;
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@@ -1745,14 +1734,16 @@ void bootloader(void)
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linkbits_last[0] = linkbits_last[1] = linkbits_last[2] = linkbits_last[3] = linkbits_last_p89 = 0;
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print_string("Detecting CPU: ");
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isRTL8373 = 0;
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reg_read_m(0x4);
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if (sfr_data[1] == 0x73) { // Register was 0x83730000
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print_string("RTL8373\n");
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isRTL8373 = 1;
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if (!machine.isRTL8373)
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print_string("INCORRECT MACHINE!");
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rtl8224_enable(); // Power on the RTL8224
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} else {
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print_string("RTL8372\n");
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if (machine.isRTL8373)
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print_string("INCORRECT MACHINE!");
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}
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// Print SW version
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@@ -1774,7 +1765,7 @@ void bootloader(void)
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uip_ipaddr(&uip_netmask, netmask[0], netmask[1], netmask[2], netmask[3]);
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REG_SET(0x7f94, 0x0);
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if (isRTL8373)
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if (machine.isRTL8373)
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rtl8373_init();
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else
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rtl8372_init();
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