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logicog
2025-05-10 15:52:02 +02:00
parent d35eaa8a49
commit c4835b7a6c
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rtl837x_sfr.h
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/* SFR control registers for switch register access */
__sfr __at(0xa0) SFR_EXEC_GO;
__sfr __at(0xa1) SFR_EXEC_STATUS;
__sfr __at(0xa2) SFR_REG_ADDRH;
__sfr __at(0xa3) SFR_REG_ADDRL;
__sfr __at(0xa4) SFR_DATA_24;
__sfr __at(0xa5) SFR_DATA_16;
__sfr __at(0xa6) SFR_DATA_8;
__sfr __at(0xa7) SFR_DATA_0;
/* SFR control registers for phy access via SMI/MDIO */
__sfr __at(0xc2) SFR_SMI_REG_H;
__sfr __at(0xc3) SFR_SMI_REG_L;
__sfr __at(0xc4) SFR_SMI_DEV;
__sfr __at(0xc5) SFR_SMI_PHYMASK;
#define SFR_SMI_PHY SFR_DATA_16
/* Extended IRQ EIE register for external interrupts */
__sfr __at(0xe8) EIE;
__sbit __at(0xe8) EX2;
__sbit __at(0xe9) EX3;
/* EXIF additional external IRQ control register */
__sfr __at(0x91) EXIF;
/* Extended IRQ EIP register for external interrupt priority */
__sfr __at(0xf8) EIP;
__sbit __at(0xf9) PX3;
/* SFR control registers for serial communication */
__sfr __at(0xc8) T2CON;
__sfr __at(0xca) RCAP2L;
__sfr __at(0xcb) RCAP2H;
/* SFR Bank control register: 0x0-3f. A value of 0 is bank 1 */
__sfr __at(0x96) SFR_BANK;
__sfr __at(0x8e) CKCON;
__sfr __at(0x97) SFR_97;
__sfr __at(0xb9) SFR_b9;
__sfr __at(0xba) SFR_ba;
/* FLASH controller SFRs */
__sfr __at(0x80) SFR_FLASH_EXEC;
__sbit __at(0x82) SFR_FLASH_EXEC_GO;
__sbit __at(0x80) SFR_FLASH_EXEC_BUSY;
__sfr __at(0xb1) SFR_FLASH_CMD_R;
__sfr __at(0xb2) SFR_FLASH_CMD;
__sfr __at(0xbc) SFR_FLASH_CONFIG;
__sfr __at(0x9b) SFR_FLASH_CONF_DIV;
__sfr __at(0x9c) SFR_FLASH_CONF_RCMD;
__sfr __at(0x9d) SFR_FLASH_DUMMYCICLES;
__sfr __at(0x9a) SFR_FLASH_MODEB;
__sfr __at(0x9e) SFR_FLASH_TLEN;
__sfr __at(0xaf) SFR_FLASH_DATA24;
__sfr __at(0xae) SFR_FLASH_DATA16;
__sfr __at(0xad) SFR_FLASH_DATA8;
__sfr __at(0xac) SFR_FLASH_DATA0;
__sfr __at(0xab) SFR_FLASH_ADDR16;
__sfr __at(0xaa) SFR_FLASH_ADDR8;
__sfr __at(0xa9) SFR_FLASH_ADDR0;