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regs: wrap REG_SET and REG_WRITE in do { } while (0)

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Both macros expand to a run of statements joined by backslashes with
nothing around them, so as the unbraced body of an if or a for only the
first assignment belongs to that body. The other three and the
reg_write() call sit after it and run once, unconditionally, with
whatever the loop counter ended on. Wrapping each macro into a single
statement is what every call site already assumes it to be.

This hands the compiler no new room around the SFR writes, which is worth
showing rather than asserting. Building the whole image before and after
and comparing the generated assembly module by module, with label
numbering, block scope suffixes and the version string normalised away,
three modules differ: rtl837x_igmp, rtl837x_port and rtl837x_leds. Ten
modules call these macros, so the other seven come out identical, and so
does everything else in the image.

Those three differ because they hold the five unbraced uses. Two of them
want a fix rather than only the brace, and that is left to the commits
that follow.

Six bytes of BANK1 on SWTGW218AS, nothing anywhere else.
This commit is contained in:
d00f
2026-08-14 07:34:42 +02:00
parent 4ff009dbfc
commit be6d47a3ab
1 changed files with 16 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
rtl837x_regs.h
+16 -8
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@@ -305,32 +305,40 @@
#ifdef REGDBG #ifdef REGDBG
#define REG_SET(r, v) SFR_DATA_24 = (((uint32_t)v) >> 24) & 0xff; \ #define REG_SET(r, v) do { \
SFR_DATA_24 = (((uint32_t)v) >> 24) & 0xff; \
SFR_DATA_16 = (((uint32_t)v) >> 16) & 0xff; \ SFR_DATA_16 = (((uint32_t)v) >> 16) & 0xff; \
SFR_DATA_8 = (((uint16_t)v) >> 8 & 0xff); \ SFR_DATA_8 = (((uint16_t)v) >> 8 & 0xff); \
SFR_DATA_0 = (v) & 0xff; \ SFR_DATA_0 = (v) & 0xff; \
reg_write(r); \ reg_write(r); \
write_char('R'); print_byte(r >> 8); print_byte(r); write_char('-'); \ write_char('R'); print_byte(r >> 8); print_byte(r); write_char('-'); \
print_byte(((v) >> 24) & 0xff); print_byte((v) >> 16 & 0xff); print_byte((v) >> 8 & 0xff); print_byte( (v) & 0xff); write_char(' '); print_byte(((v) >> 24) & 0xff); print_byte((v) >> 16 & 0xff); print_byte((v) >> 8 & 0xff); print_byte( (v) & 0xff); write_char(' '); \
} while (0)
#define REG_WRITE(r, v24, v16, v8, v0) SFR_DATA_24 = (v24); \ #define REG_WRITE(r, v24, v16, v8, v0) do { \
SFR_DATA_24 = (v24); \
SFR_DATA_16 = (v16); \ SFR_DATA_16 = (v16); \
SFR_DATA_8 = (v8); \ SFR_DATA_8 = (v8); \
SFR_DATA_0 = (v0); \ SFR_DATA_0 = (v0); \
reg_write(r); \ reg_write(r); \
write_char('R'); print_byte(r>>8); print_byte(r); write_char('-'); print_byte(v24); print_byte(v16); print_byte(v8); print_byte(v0); write_char(' '); write_char('R'); print_byte(r>>8); print_byte(r); write_char('-'); print_byte(v24); print_byte(v16); print_byte(v8); print_byte(v0); write_char(' '); \
} while (0)
#else #else
#define REG_SET(r, v) SFR_DATA_24 = (((uint32_t)v) >> 24) & 0xff; \ #define REG_SET(r, v) do { \
SFR_DATA_24 = (((uint32_t)v) >> 24) & 0xff; \
SFR_DATA_16 = (((uint32_t)v) >> 16) & 0xff; \ SFR_DATA_16 = (((uint32_t)v) >> 16) & 0xff; \
SFR_DATA_8 = (((uint16_t)v) >> 8 & 0xff); \ SFR_DATA_8 = (((uint16_t)v) >> 8 & 0xff); \
SFR_DATA_0 = (v) & 0xff; \ SFR_DATA_0 = (v) & 0xff; \
reg_write(r); reg_write(r); \
} while (0)
#define REG_WRITE(r, v24, v16, v8, v0) SFR_DATA_24 = (v24); \ #define REG_WRITE(r, v24, v16, v8, v0) do { \
SFR_DATA_24 = (v24); \
SFR_DATA_16 = (v16); \ SFR_DATA_16 = (v16); \
SFR_DATA_8 = (v8); \ SFR_DATA_8 = (v8); \
SFR_DATA_0 = (v0); \ SFR_DATA_0 = (v0); \
reg_write(r); reg_write(r); \
} while (0)
#endif #endif
#endif #endif