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More documentation on the L2 table

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logicog
2025-07-13 23:15:51 +02:00
parent e3bb76ec1b
commit ba1b03dd63
1 changed files with 17 additions and 3 deletions
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doc/l2.md
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@@ -23,16 +23,30 @@ TT: 04: TBL_L2_UNICAST, 03: TBL_VLAN
An entry is retrieved from the tables by setting the data in registers to the
desired entry filter, then executing a table command by writing to RTL837X_TBL_CTRL
with execute bit 0 set, table type set and entry identifier (VLAN-Id or hash for L2).
Data then is in the output data registers
Data will be fetched from the table and is available once the execute bit has been
cleared by the ASIC. Data then is in the output data registers
```
#define RTL837x_L2_DATA_OUT_A 0x5ccc
#define RTL837x_L2_DATA_OUT_B 0x5cd0
#define RTL837x_L2_DATA_OUT_C 0x5cd4
DATA_OUT_A DATA_OUT_B L2_DATA_OUT_C
M2 M3 M4 M5 fV VV M0 M1 xx xF xx xg
M0-M5: 6 bytes of MAC, M0 is MSB
V: 12 bits of VLAN-ID
f: bit 5 set: Entry is valid, otherwise stale
bit 6: bit 0 of port-number
bit 7: bit 1 of port-number
g: bit 0: bit 2 of port-number
bit 1: bit 3 of port-number (MSB)
F: bit 0: entry is static(1) or learned (0)
```
The next entry can be now found in RTL837x_TBL_DATA_0 (entry = RTL837x_TBL_DATA_0_bits(0-11) + 1),
which can be used to get the next entry by writing this value to RTL837X_TBL_CTRL.
which can be used to get the next entry by writing this value to RTL837X_TBL_CTRL
and executing again for the given table type. This entry number is probably a hash, for which
the algorithm is unknown.
Deleting the entire L2 table is done by checking and setting 0x53dc to 0x0, then writing
0x00010000 to register RTL837x_L2_TBL_CTRL and waiting until the bit 16 that was