diff --git a/rtl837x_sfr.h b/rtl837x_sfr.h
index 46e5a86..71fc4ae 100644
--- a/rtl837x_sfr.h
+++ b/rtl837x_sfr.h
@@ -21,6 +21,7 @@ __sfr __at(0xa7) SFR_DATA_0;
 #define SFR_EXEC_WRITE_SMI 11
 
 /* SFR control registers for phy access via SMI/MDIO */
+__sfr16 __at(0xc2c3) SFR_SMI_REG_U16;
 __sfr __at(0xc2) SFR_SMI_REG_H;
 __sfr __at(0xc3) SFR_SMI_REG_L;
 __sfr __at(0xc4) SFR_SMI_DEV;
diff --git a/rtlplayground.c b/rtlplayground.c
index 37ac990..47f83d7 100644
--- a/rtlplayground.c
+++ b/rtlplayground.c
@@ -505,8 +505,7 @@ void sds_write_v(uint8_t sds_id, uint8_t page, uint8_t reg, uint16_t v)
 	print_string("Q"); print_byte(sds_id); print_byte(page); print_byte(reg);
 	write_char(':'); print_byte(v >> 8); print_byte(v); write_char(' ');
 #endif
-	SFR_DATA_8 = v >> 8;
-	SFR_DATA_0 = v;
+	SFR_DATA_U16 = v;
 	SFR_93 = reg;
 	SFR_94 = page << 1 | sds_id;
 	SFR_EXEC_GO = SFR_EXEC_WRITE_SDS;
@@ -1086,11 +1085,11 @@ void phy_write_mask(uint16_t phy_mask, uint8_t dev_id, uint16_t reg, uint16_t v)
 	print_string("P"); print_byte(phy_mask>>8); print_byte(phy_mask); print_byte(dev_id); write_char('.'); print_byte(reg>>8); print_byte(reg); write_char(':');
 	print_byte(v>>8); print_byte(v); write_char(' ');
 #endif
-	SFR_DATA_8 = v >> 8;			// SFR_A6
-	SFR_DATA_0 = v;				// SFR_A7
+	SFR_DATA_U16 = v ;			    // SFR_A6, SFR_A7
+
 	SFR_SMI_PHYMASK = phy_mask;		// SFR_C5
-	SFR_SMI_REG_H = reg >> 8;		// SFR_C2
-	SFR_SMI_REG_L = reg;			// SFR_C3
+	SFR_SMI_REG_U16 = reg;			// SFR_C2, SFR_C3
+
 	SFR_SMI_DEV = (phy_mask >> 8) | dev_id  << 3 | 2; // SFR_C4: bit 2 can also be set for some option
 	SFR_EXEC_GO = SFR_EXEC_WRITE_SMI;
 	do {
@@ -1132,8 +1131,8 @@ void phy_read(uint8_t phy_id, uint8_t dev_id, uint16_t reg)
 #ifdef REGDBG
 	print_string("p"); print_byte(phy_id); print_byte(dev_id); write_char('.'); print_byte(reg>>8); print_byte(reg); write_char(':');
 #endif
-	SFR_SMI_REG_H = reg >> 8;	// c3
-	SFR_SMI_REG_L = reg;		// c2
+	SFR_SMI_REG_U16 = reg;		// c2, c2
+
 	SFR_SMI_PHY = phy_id;		// a5
 	SFR_SMI_DEV = dev_id << 3 | 2;	// c4
 
@@ -1208,9 +1207,7 @@ void sds_init(void)
 	p001e.000d:0010 p001e.000d:0010	R02f8-00000010 R02f4-00000010 P000001.1e00000d:b7fe
 */
 	phy_read(0, 0x1e, 0xd);
-	uint16_t pval = SFR_DATA_8;
-	pval <<= 8;
-	pval |= SFR_DATA_0;
+	uint16_t pval = SFR_DATA_U16;
 
 	// PHY Initialization:
 	REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
@@ -1224,9 +1221,7 @@ void sds_init(void)
 	phy_write_mask(0x1, 0x1e, 0xd, pval);
 
 	phy_read(0, 0x1e, 0xd);
-	pval = SFR_DATA_8;
-	pval <<= 8;
-	pval |= SFR_DATA_0;
+	pval = SFR_DATA_U16;
 
 	REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
 
@@ -1408,15 +1403,15 @@ void rtl8373_init(void)
 
 	// q000601:c800 Q000601:c804 q000601:c804 Q000601:c800
 	sds_read(0, 0x06, 0x01);
-	uint16_t pval = SFR_DATA_8;
-	pval <<= 8;
-	pval |= SFR_DATA_0;
+	uint16_t pval = SFR_DATA_U16;
+
+
 	sds_write_v(0, 0x06, 0x01, pval | 0x04);
 	delay(50);
 	sds_read(0, 0x06, 0x01);
-	pval = SFR_DATA_8;
-	pval <<= 8;
-	pval |= SFR_DATA_0;
+	pval = SFR_DATA_U16;
+
+
 	sds_write_v(0, 0x06, 0x01, pval & 0xfffb);
 
 	phy_config_8224();
@@ -1430,9 +1425,9 @@ void rtl8373_init(void)
 	sds_write_v(1, 0x36, 0x05, 0x4000);
 	sds_write_v(1, 0x1f, 0x02, 0x001f);
 	sds_read(1, 0x1f, 0x15);
-	pval = SFR_DATA_8;
-	pval <<= 8;
-	pval |= SFR_DATA_0;
+	pval = SFR_DATA_U16;
+
+
 
 	// r0a90:000000f3 R0a90-000000fc
 	reg_read_m(0xa90);