mirror of
https://github.com/logicog/RTLPlayground.git
synced 2026-08-30 14:52:51 +08:00
N-type SOC need to swap some Serdes lines to make it work.
Without this fix N-type SOC devices like RTL8372N, RTL8383N and also the 4-port PHY RTL8224N, don't have a functional Serdes. Although the SOC sees a link, there is no packet flow on both SFP-port nor RTL8224 ports. Added helper functions to read/write to the RTL8224. RTL8224 has the same register layout so we can use the same register defines as for the main SOC.
This commit is contained in:
René van Dorst
+98
-5
@@ -8,6 +8,7 @@
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// Phy ID of the external RTL8224 PHY.
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#define RTL8224_PHY_ID 0x00
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#define RTL8224_DEV_ID 0x1e
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#include <stdint.h>
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#include "rtl837x_common.h"
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@@ -15,14 +16,17 @@
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#include "rtl837x_regs.h"
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#include "rtl837x_phy.h"
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#include "phy.h"
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#include "machine.h"
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#pragma codeseg BANK2
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#pragma constseg BANK2
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extern __code uint16_t bit_mask[16];
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extern __code const struct machine machine;
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extern __xdata struct machine_runtime machine_detected;
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__code uint16_t rtl8224_ca[42] = {
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// SDS_DATA, SDS_CMD
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0x4480, 0xc842,
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0x0400, 0xc9c2,
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0x6d02, 0xcc42,
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@@ -43,6 +47,9 @@ __code uint16_t rtl8224_ca[42] = {
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0xabb0, 0xcedc,
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0x5078, 0xc90c,
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0xc45c, 0xc18c,
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// Note Swapping the RX for N-device here, don't work
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// Setting will apply but still no packets flow.
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// 0x2000, 0xc10c,
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0, 0
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};
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@@ -75,19 +82,24 @@ void rtl8224_phy_enable(void) __banked
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// p001e.0a90:00f3 R02f8-000000f3 R02f4-000000fc P000001.1e000a90:00fc
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print_string("\r\nrtl8224_phy_enable called\r\n");
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phy_read(RTL8224_PHY_ID, 0x1e, 0xa90);
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phy_read(RTL8224_PHY_ID, RTL8224_DEV_ID, RTL837X_CFG_PHY_MDI_REVERSE);
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pval = SFR_DATA_U16;
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// PHY Initialization:
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REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
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pval &= 0xfff0;
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pval |= 0x0c;
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REG_WRITE(0x2f4, 0, 0, pval >> 8, pval);
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phy_write(RTL8224_PHY_ID, 0x1e, 0xa90, pval);
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phy_write(RTL8224_PHY_ID, RTL8224_DEV_ID, RTL837X_CFG_PHY_MDI_REVERSE, pval);
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delay(50);
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if (machine_detected.isN) {
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print_string(" N-settings");
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// TX_POLARITY_SWAP
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rtl8224_write_reg_u16(RTL837X_CFG_PHY_TX_POLARITY_SWAP, 0x596A);
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}
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print_string("\r\nrtl8224_phy_enable done\r\n");
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}
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@@ -153,7 +165,15 @@ void phy_config(uint8_t phy) __banked
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void phy_config_8224(void) __banked
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{
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uint16_t pval;
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print_string("\r\nphy_config_8224 called\r\n");
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print_string("\r\nphy_config_8224 called\r\nRTL8224 ID: ");
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// Print RTL8224 chip id
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rtl8224_read_reg_u16(RTL837X_REG_CHIP_ID + 1);
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print_short(SFR_DATA_U16);
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rtl8224_read_reg_u16(RTL837X_REG_CHIP_ID);
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print_byte(SFR_DATA_U16 >> 8);
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print_byte(SFR_DATA_U16);
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write_char('\n');
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// p001e.7b20:0bff R02f8-00000bff R02f4-00000bed P000001.1e007b20:0bed
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phy_read(RTL8224_PHY_ID, 0x1e, 0x7b20);
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@@ -437,3 +457,76 @@ void phy_reset(uint8_t port) __banked
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// Re-enable PHY
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phy_write(port, PHY_MMD_CTRL, 0xa610, v & 0xf7ff);
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}
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// Read RTL8224 register.
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// Registers names are the same as on the RTL837x.
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// Reading only reads the lower 16-bit part of the 32-bit register.
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// When also needing read the upper 16-bits, use register address + 1.
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// Readed values it return via sfr-data.
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void inline rtl8224_read_reg_u16(uint16_t reg) __banked
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{
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// void phy_read(uint8_t phy_id, uint8_t dev_id, uint16_t reg)
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// phy_read(RTL8224_PHY_ID, 0x1e, reg);
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SFR_SMI_REG_U16 = reg; // c2, c2
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SFR_SMI_PHY = RTL8224_PHY_ID; // a5
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SFR_SMI_DEV = RTL8224_DEV_ID << 3 | 2; // c4
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SFR_EXEC_GO = SFR_EXEC_READ_SMI;
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do {
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} while (SFR_EXEC_STATUS != 0);
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}
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// Write RTL8224 register.
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// Registers names are the same as on the RTL837x.
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// Writing only the lower 16-bit part of the 32-bit register.
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// When also needing to write the upper 16-bits, use register address + 1.
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void inline rtl8224_write_reg_u16(uint16_t reg, uint16_t val) __banked
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{
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SFR_DATA_U16 = val; // SFR_A6, SFR_A7
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SFR_SMI_REG_U16 = reg; // SFR_C2, SFR_C3
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//void phy_write(uint8_t phy_id, uint8_t dev_id, uint16_t reg, uint16_t v)
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// phy_write(RTL8224_PHY_ID, 0x1e, reg, val);
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uint16_t phy_mask = bit_mask[RTL8224_PHY_ID];
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SFR_SMI_PHYMASK = phy_mask; // SFR_C5
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SFR_SMI_DEV = (phy_mask >> 8) | RTL8224_DEV_ID << 3 | 2; // SFR_C4: bit 2 can also be set for some option
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SFR_EXEC_GO = SFR_EXEC_WRITE_SMI;
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do {
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} while (SFR_EXEC_STATUS != 0);
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}
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// // Modify RTL8224 register.
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// // Registers names are the same as on the RTL837x.
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// // Modifies only the lower 16-bit part of the 32-bit register.
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// // When also needing to modifie the upper 16-bits, use register address + 1.
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// void rtl8224_modify_reg_u16(uint16_t reg, uint16_t clear, uint16_t set) __banked
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// {
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// phy_read(RTL8224_PHY_ID, 0x1e, reg);
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// uint16_t pval = SFR_DATA_U16;
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// pval &= ~(clear);
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// pval |= set;
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// phy_write(RTL8224_PHY_ID, 0x1e, reg, pval);
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// }
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// Write to the RTL8224 SDS registers.
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void rtl8224_sds_write(uint16_t sds_cmd, uint16_t value) __banked
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{
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// Wait for command bit is cleared
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do {
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rtl8224_read_reg_u16(RTL837X_SDS_INDACS_CMD);
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} while (SFR_DATA_8 & 0x80);
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rtl8224_write_reg_u16(RTL837X_SDS_INDACS_WRITE_DATA, value);
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rtl8224_write_reg_u16(RTL837X_SDS_INDACS_CMD, sds_cmd);
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// Wait for command bit is cleared
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do {
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rtl8224_read_reg_u16(RTL837X_SDS_INDACS_CMD);
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} while (SFR_DATA_8 & 0x80);
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}
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@@ -17,5 +17,15 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked;
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void phy_set_duplex(uint8_t port, uint8_t fullduplex) __banked;
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void phy_show(uint8_t port) __banked;
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void phy_reset(uint8_t port) __banked;
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void rtl8224_read_reg_u16(uint16_t reg) __banked;
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void rtl8224_write_reg_u16(uint16_t reg, uint16_t val) __banked;
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void rtl8224_sds_write(uint16_t sds_cmd, uint16_t val) __banked;
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#define RTL8224_SDS_WRITE(sds_id, page, reg, v) uint16_t _sdscmd = (uint16_t)(sds_id & 0x01) | (1 << 14) | (1 << 15); \
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_sdscmd |= (page & 0x3F) << 1; \
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_sdscmd |= ((uint16_t)(reg & 0x1f)) << 7; \
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print_string("CMD: "); print_short(_sdscmd); \
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write_char('-'); print_short(v); \
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rtl8224_sds_write(_sdscmd, v);
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#endif
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@@ -36,7 +36,20 @@
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#define RTL837X_REG_SEC_COUNTER2 0x06f8
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// Used for counting seconds
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/*
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* SDS
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*/
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#define RTL837X_SDS_INDACS_CMD 0x3F8
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#define RTL837X_SDS_INDACS_WRITE_DATA 0x400
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#define RTL837X_REG_SDS_MODES 0x7b20
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/*
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* PHY
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*/
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#define RTL837X_CFG_PHY_TX_POLARITY_SWAP 0xA94
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#define RTL837X_CFG_PHY_MDI_REVERSE 0xA90
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/*
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* 5 Bits each give the state of the 2 SerDes of the RTL8372
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* Values are:
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+47
-5
@@ -1403,6 +1403,39 @@ void sds_init(void)
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REG_WRITE(0x2f4, 0, 0, pval >> 8, pval);
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phy_write_mask(0x1, 0x1e, 0xd, pval);
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if (machine_detected.isN) {
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uint16_t pval;
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print_string(" N-settings");
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// Serdes 0 RX PN swap for 64B/66B
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sds_read(1, 6, 2);
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pval = SFR_DATA_U16;
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sds_write_v(1, 6, 2, pval | 0x2000);
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// Serdes 1 RX PN swap for 8B/10B
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sds_read(1, 0, 0);
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pval = SFR_DATA_U16;
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sds_write_v(1, 0, 0, pval | 0x200);
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// Serdes 0 RX PN swap for 64B/66B
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sds_read(0, 6, 2);
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pval = SFR_DATA_U16;
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sds_write_v(0, 6, 2, pval | 0x2000);
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if (machine_detected.isRTL8373) {
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// RTL8224: Serdes 0 RX PN swap for 64B/66B
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// We assume that RTL8373N always paired with RTL8224N.
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// This sds register value is 0x0000 at reset.
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// So only write to it.
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RTL8224_SDS_WRITE(0, 6, 2, 0x2000);
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} else {
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// Serdes 0 RX PN swap for 8B/10B
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sds_read(0, 0, 0);
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pval = SFR_DATA_U16;
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sds_write_v(0, 0, 0, pval | 0x200);
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}
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}
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}
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@@ -1549,9 +1582,18 @@ void rtl8373_init(void)
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pval = SFR_DATA_U16;
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// r0a90:000000f3 R0a90-000000fc
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reg_read_m(0xa90);
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reg_read_m(RTL837X_CFG_PHY_MDI_REVERSE);
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sfr_mask_data(0, 0x0f,0x0c);
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reg_write_m(0xa90);
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reg_write_m(RTL837X_CFG_PHY_MDI_REVERSE);
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if (machine_detected.isN) {
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print_string(" TX_POLARITY_SWAP\n");
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// FOR N-Version: #TX_POLARITY_SWAP
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reg_read_m(RTL837X_CFG_PHY_TX_POLARITY_SWAP);
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sfr_data[2] = 0x59;
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sfr_data[3] = 0x6a;
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reg_write_m(RTL837X_CFG_PHY_TX_POLARITY_SWAP);
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}
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rtl8224_phy_enable();
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@@ -1617,9 +1659,9 @@ void rtl8372_init(void)
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reg_write_m(RTL837X_REG_SDS_MODES);
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// r0a90:000000f3 R0a90-000000fc
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reg_read_m(0xa90);
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sfr_mask_data(0, 0x0f,0x0c);
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reg_write_m(0xa90);
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reg_read_m(RTL837X_CFG_PHY_MDI_REVERSE);
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sfr_mask_data(0, 0x0f, 0x0c);
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reg_write_m(RTL837X_CFG_PHY_MDI_REVERSE);
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// Disable PHYs for configuration
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phy_write_mask(0xf0,0x1f,0xa610,0x2858);
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