From aba69cd6405e8e8248db03c059c5c42f71097365 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= <opensource@vdorst.com>
Date: Sun, 30 Aug 2026 20:40:21 +0200
Subject: [PATCH] DHCP: Added workarounds for SDCC bug 4070

---
 dhcp.c          |  7 ++++++-
 rtlplayground.c | 23 +++++++++++++++++++----
 2 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/dhcp.c b/dhcp.c
index ad5c536..d821f80 100644
--- a/dhcp.c
+++ b/dhcp.c
@@ -351,7 +351,12 @@ void dhcp_start(void) __banked
 		return;
 	}
 	get_random_32();
-	dhcp_state.transaction_id = SFR_DATA_U32;
+	// Workaround SDCC bug 4070: dhcp_state.transaction_id = SFR_DATA_U32;
+	__xdata uint8_t * tid = &dhcp_state.transaction_id;
+	*tid++ = SFR_DATA_24;
+	*tid++ = SFR_DATA_16;
+	*tid++ = SFR_DATA_8;
+	*tid = SFR_DATA_0;
 	dhcp_state.state = DHCP_START;
 	print_string("dhcp_start done\n");
 }
diff --git a/rtlplayground.c b/rtlplayground.c
index cd5e14e..a4c133d 100644
--- a/rtlplayground.c
+++ b/rtlplayground.c
@@ -1813,6 +1813,12 @@ void init_smi(void)
 	/* Set the SMI(i.e.I2C) type for PHY polling, 0b01 is 2.5/10G PHY. Disable (0b00) for the SFP-ports
 	 * which are at port 8 and additionally at port 3 for a dual SFP device
 	 */
+
+	// using 16bit value, because it can load cheap.
+	// Default: 0x00005555
+	// Workaround for SDCC BUG 4070: SFR_DATA_U32 = 0x00005555;
+	SFR_DATA_U16_UPPER = 0x0000;
+	SFR_DATA_U16= 05555;
 	if (machine.n_10g == 2) {
 		REG_SET(RTL837X_REG_SMI_MAC_TYPE, 0x00015555);
 	} else {
@@ -1820,11 +1826,20 @@ void init_smi(void)
 	}
 
 	// Configure polling of all PHYs by the MAC to detect link-state changes
-	if (machine_detected.isRTL8373) {
-		REG_SET(RTL837X_REG_SMI_PORT_POLLING, 0xff);
-	} else {
-		REG_SET(RTL837X_REG_SMI_PORT_POLLING, machine.n_sfp == 2 ? 0xf0 : 0x1f8);
+	// Default: 0x000000ff
+	// Workaround for SDCC BUG 4070: SFR_DATA_U32 = 0x000000ff;
+	SFR_DATA_U16_UPPER = 0x0000;
+	SFR_DATA_U16= 0x00ff;
+	if (!machine_detected.isRTL8373) {
+		if (machine.n_sfp == 2) {
+			SFR_DATA_0 = 0xf0;
+		} else {
+			SFR_DATA_0 = 0xf8;
+			SFR_DATA_16 = 0x1f;
+		}
 	}
+	reg_write(RTL837X_REG_SMI_PORT_POLLING);
+
 	// Enable MDC
 	reg_read_m(RTL837X_REG_SMI_CTRL);
 	sfr_mask_data(1, 0, 0x70); 	// Set bits 12-14 to enable MDC for SMI0-SMI2