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https://github.com/logicog/RTLPlayground.git
synced 2026-08-30 14:52:51 +08:00
Adding support for 2.5Gbit Ethernet modules
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@@ -24,6 +24,7 @@
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#define SDS_SGMII 0x02
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#define SDS_SGMII 0x02
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#define SDS_1000BX_FIBER 0x04
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#define SDS_1000BX_FIBER 0x04
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#define SDS_HISGMII 0x12
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#define SDS_HISGMII 0x12
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#define SDS_HSG 0x16
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#define SDS_10GR 0x1a
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#define SDS_10GR 0x1a
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#define RTL837X_REG_LINKS 0x63f0
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#define RTL837X_REG_LINKS 0x63f0
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+27
-6
@@ -441,7 +441,7 @@ void sds_config(uint8_t sds, uint8_t mode)
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if (mode == SDS_10GR) // 10G Fiber
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if (mode == SDS_10GR) // 10G Fiber
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sds_write_v(sds, 0x21, 0x10, 0x4480); // Q002110:6480
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sds_write_v(sds, 0x21, 0x10, 0x4480); // Q002110:6480
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else
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else
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sds_write_v(sds, 0x21, 0x10, 0x6400); // Q002110:6480
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sds_write_v(sds, 0x21, 0x10, 0x6480); // Q002110:6480
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sds_write_v(sds, 0x21, 0x13, 0x0400); // Q002113:0400
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sds_write_v(sds, 0x21, 0x13, 0x0400); // Q002113:0400
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sds_write_v(sds, 0x21, 0x18, 0x6d02); // Q002118:6d02
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sds_write_v(sds, 0x21, 0x18, 0x6d02); // Q002118:6d02
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sds_write_v(sds, 0x21, 0x1b, 0x424e); // Q00211b:424e
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sds_write_v(sds, 0x21, 0x1b, 0x424e); // Q00211b:424e
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@@ -462,6 +462,7 @@ void sds_config(uint8_t sds, uint8_t mode)
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page = 0x24;
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page = 0x24;
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break;
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break;
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case SDS_HISGMII:
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case SDS_HISGMII:
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case SDS_HSG:
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SFR_DATA_8 = 0x02;
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SFR_DATA_8 = 0x02;
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page = 0x28;
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page = 0x28;
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break;
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break;
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@@ -533,6 +534,14 @@ uint8_t sfp_read_reg(uint8_t reg)
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return sfr_data[3];
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return sfr_data[3];
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}
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}
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// Sleep the given number of ticks without doing housekeeping
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void delay(uint16_t t)
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{
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sleep_until = ticks + t;
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while (sleep_until >= ticks)
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PCON |= 1;
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}
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//
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//
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// An idle function that sleeps for 1 tick and does all the house-keeping
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// An idle function that sleeps for 1 tick and does all the house-keeping
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@@ -588,11 +597,10 @@ void idle(void)
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print_string("\r\n<MODULE INSERTED> ");
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print_string("\r\n<MODULE INSERTED> ");
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// Read Reg 11: Encoding, see SFF-8472 and SFF-8024
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// Read Reg 11: Encoding, see SFF-8472 and SFF-8024
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// Read Reg 12: Signalling rate (including overhead) in 100Mbit: 0xd: 1Gbit, 0x67:10Gbit
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// Read Reg 12: Signalling rate (including overhead) in 100Mbit: 0xd: 1Gbit, 0x67:10Gbit
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delay(100); // Delay, because some modules need some time to wake up
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uint8_t rate = sfp_read_reg(12);
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uint8_t rate = sfp_read_reg(12);
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print_string("\r\nRate: ");
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print_string("\r\nRate: "); print_byte(rate);
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print_byte(rate);
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print_string(" Encoding: "); print_byte(sfp_read_reg(11));
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print_string("\r\nEncoding: ");
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print_byte(sfp_read_reg(11));
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print_string("\r\n");
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print_string("\r\n");
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for (uint8_t i = 20; i < 60; i++) {
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for (uint8_t i = 20; i < 60; i++) {
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uint8_t c = sfp_read_reg(i);
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uint8_t c = sfp_read_reg(i);
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@@ -602,6 +610,8 @@ void idle(void)
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print_string("\r\n");
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print_string("\r\n");
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if (rate == 0xd)
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if (rate == 0xd)
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sds_config(1, SDS_1000BX_FIBER);
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sds_config(1, SDS_1000BX_FIBER);
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if (rate == 0x1f) // Ethernet 2.5 GBit
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sds_config(1, SDS_HSG);
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if (rate > 0x65 && rate < 0x70)
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if (rate > 0x65 && rate < 0x70)
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sds_config(1, SDS_10GR);
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sds_config(1, SDS_10GR);
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@@ -627,7 +637,7 @@ void idle(void)
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void sleep(uint16_t t)
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void sleep(uint16_t t)
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{
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{
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sleep_until = ticks + t;
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sleep_until = ticks + t;
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while (sleep_until <= ticks)
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while (sleep_until >= ticks)
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idle();
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idle();
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}
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}
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@@ -1348,6 +1358,17 @@ void bootloader(void)
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print_string("\r\nRESET\n\n");
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print_string("\r\nRESET\n\n");
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reset_chip();
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reset_chip();
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}
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}
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if (cmd_compare(0, "sfp")) {
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uint8_t rate = sfp_read_reg(12);
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print_string("\r\nRate: "); print_byte(rate);
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print_string(" Encoding: "); print_byte(sfp_read_reg(11));
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print_string("\r\n");
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for (uint8_t i = 20; i < 60; i++) {
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uint8_t c = sfp_read_reg(i);
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if (c)
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write_char(c);
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}
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}
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if (cmd_compare(0, "flash") && cmd_words_b[1] > 0 && sbuf[cmd_words_b[1]] == 'd') {
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if (cmd_compare(0, "flash") && cmd_words_b[1] > 0 && sbuf[cmd_words_b[1]] == 'd') {
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print_string("\r\nDUMPING FLASH\r\n");
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print_string("\r\nDUMPING FLASH\r\n");
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flash_dump(0, 255);
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flash_dump(0, 255);
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