From 9a3f8c359de3882fad28feeb30b45bbcf1380ffc Mon Sep 17 00:00:00 2001
From: logicog <git@logicog.de>
Date: Fri, 17 Apr 2026 19:11:44 +0200
Subject: [PATCH] Enable 10g EEE on init

---
 rtl837x_init.c |  8 ++++----
 rtl837x_port.c | 21 +++++++++++++++------
 2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/rtl837x_init.c b/rtl837x_init.c
index 1a2e856..50d94f6 100644
--- a/rtl837x_init.c
+++ b/rtl837x_init.c
@@ -91,7 +91,7 @@ void static sds_init(void)
 }
 
 
-void rtl8373_init(void)
+void rtl8373_init(void) __banked
 {
 	print_string("\nrtl8373_init called\n");
 
@@ -168,7 +168,7 @@ void rtl8373_init(void)
 
 	reg_bit_set(RTL837X_REG_HW_CONF, 0);
 
-	// enable EEE for all ports at 2.5G and 10G, but don't reset the PHYs
+	// enable EEE for all ports at 2.5G, but don't reset the PHYs
 	port_eee_enable_all(EEE_2G5 | EEE_NORESET);
 
 	// TODO: patch the PHYs
@@ -188,7 +188,7 @@ void rtl8373_init(void)
 }
 
 
-void rtl8372_init(void)
+void rtl8372_init(void) __banked
 {
 	print_string("\nrtl8372_init called\n");
 
@@ -246,7 +246,7 @@ void rtl8372_init(void)
 
 
 	// enable EEE for all ports at 2.5G and 10G, but don't reset the PHYs
-	port_eee_enable_all(EEE_2G5 | EEE_NORESET);
+	port_eee_enable_all(EEE_10G | EEE_NORESET);
 	
 	// TODO: patch the PHYs
 
diff --git a/rtl837x_port.c b/rtl837x_port.c
index 437f550..635bac0 100644
--- a/rtl837x_port.c
+++ b/rtl837x_port.c
@@ -495,7 +495,7 @@ void port_eee_enable(__xdata uint8_t port,__xdata uint8_t speed) __banked
 	REG_SET(RTL837X_EEE_CTRL_BASE + (port << 8), EEE_RX_ENABLE | EEE_TX_ENABLE);
 	print_string("EEE on for "); print_byte(port); print_string(" speed "); 
 	// Enable all speeds up to the specified speed
-	if ((speed & (EEE_100 | EEE_1000 | EEE_2G5 | EEE_5G | EEE_10G)) == EEE_100) {
+	if (speed & EEE_100) {
 			print_string("100m\n");
 			// Enable EEE advertisement for 100BASE-T via EEE Advertisement Reg
 			phy_write(port, PHY_MMD_AN, PHY_EEE_ADV, PHY_EEE_BIT_100M);
@@ -503,7 +503,7 @@ void port_eee_enable(__xdata uint8_t port,__xdata uint8_t speed) __banked
 				phy_reset(port);
 			return;
 	}
-	if ((speed & (EEE_100 | EEE_1000 | EEE_2G5 | EEE_5G | EEE_10G)) == EEE_1000) {
+	if (speed & EEE_1000) {
 			print_string("1g\n");
 			// Disable EEE advertisement for 2.5GBASE-T via EEE Advertisement Reg 2
 			phy_write(port, PHY_MMD_AN, PHY_EEE_ADV2, 0);
@@ -513,7 +513,7 @@ void port_eee_enable(__xdata uint8_t port,__xdata uint8_t speed) __banked
 				phy_reset(port);
 			return;
 	}
-	if ((speed & (EEE_100 | EEE_1000 | EEE_2G5 | EEE_5G | EEE_10G)) == EEE_2G5) {
+	if (speed & EEE_2G5) {
 			print_string("2g5\n");
 			// Enable EEE advertisement for 100/1000BASE-T via EEE Advertisement Reg
 			phy_write(port, PHY_MMD_AN, PHY_EEE_ADV, PHY_EEE_BIT_1G | PHY_EEE_BIT_100M);
@@ -523,7 +523,7 @@ void port_eee_enable(__xdata uint8_t port,__xdata uint8_t speed) __banked
 				phy_reset(port);
 			return;
 	}
-	if ((speed & (EEE_100 | EEE_1000 | EEE_2G5 | EEE_5G | EEE_10G)) == EEE_5G) {
+	if (speed & EEE_5G) {
 			print_string("5g\n");
 			// Enable EEE advertisement for 100/1000BASE-T via EEE Advertisement Reg
 			phy_write(port, PHY_MMD_AN, PHY_EEE_ADV, PHY_EEE_BIT_1G | PHY_EEE_BIT_100M);
@@ -533,7 +533,7 @@ void port_eee_enable(__xdata uint8_t port,__xdata uint8_t speed) __banked
 				phy_reset(port);
 			return;
 	}
-	if ((speed & (EEE_100 | EEE_1000 | EEE_2G5 | EEE_5G | EEE_10G)) == EEE_10G) {
+	if (speed & EEE_10G) {
 			print_string("10g\n");
 			// Enable EEE advertisement for 100/1000BASE-T via EEE Advertisement Reg
 			phy_write(port, PHY_MMD_AN, PHY_EEE_ADV, PHY_EEE_BIT_10G | PHY_EEE_BIT_1G | PHY_EEE_BIT_100M);
@@ -650,7 +650,16 @@ void port_eee_status(uint8_t port) __banked
 void port_eee_enable_all(__xdata uint8_t speed) __banked
 {
 	for (uint8_t i = machine.min_port; i <= machine.max_port; i++) {
-		port_eee_enable(i, speed);
+		if (i == 3 && machine.n_10g) {
+			port_eee_enable(i, speed);
+		} else if (i == 8 && machine.n_10g == 2) {
+			port_eee_enable(i, speed);
+		} else {
+			if (speed & EEE_10G)
+				port_eee_enable(i, speed & EEE_NORESET | EEE_2G5);
+			else
+				port_eee_enable(i, speed);
+		}
 	}
 }