From 94cf079fcb30608f1be5a37f6b4f25180c2de2f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= Date: Sun, 31 Aug 2025 21:25:16 +0200 Subject: [PATCH] PHY: also use SFR_DATA_U16. Again less error prone and easier to read. Also see a lot of better optimalizations. A snipped. 390c390 < ;pval Allocated to registers r3 r4 --- > ;pval Allocated to registers 838,852c838,844 < ; rtl837x_phy.c:181: pval = SFR_DATA_8 & 0xbf; < mov r7,_SFR_DATA_8 < anl ar7,#0xbf < ; rtl837x_phy.c:182: pval <<= 8; < mov ar4,r7 < mov r7,#0x00 < ; rtl837x_phy.c:183: pval |= SFR_DATA_0; < mov r2,_SFR_DATA_0 < mov r3,#0x00 < mov a,r2 < orl a,r7 < mov _phy_write_PARM_4,a < mov a,r3 < orl a,r4 < mov (_phy_write_PARM_4 + 1),a --- > ; rtl837x_phy.c:181: pval = SFR_DATA_U16 & 0xbfff; > mov r4,((_SFR_DATA_U16 >> 0) & 0xFF) > mov a,#0xbf > anl a,((_SFR_DATA_U16 >> 8) & 0xFF) > mov r7,a > mov _phy_write_PARM_4,r4 > mov (_phy_write_PARM_4 + 1),r7 864c856 < mov _phy_write_PARM_3,r7 --- > mov _phy_write_PARM_3,#0x00 --- rtl837x_phy.c | 61 +++++++++++++++++++-------------------------------- 1 file changed, 22 insertions(+), 39 deletions(-) diff --git a/rtl837x_phy.c b/rtl837x_phy.c index 65b9d54..fbceb67 100644 --- a/rtl837x_phy.c +++ b/rtl837x_phy.c @@ -69,10 +69,11 @@ void rtl8224_phy_enable(void) __banked // p001e.0a90:00f3 R02f8-000000f3 R02f4-000000fc P000001.1e000a90:00fc print_string("\r\nrtl8224_phy_enable called\r\n"); phy_read(0, 0x1e, 0xa90); - uint16_t pval = SFR_DATA_8; - pval <<= 8; - pval |= SFR_DATA_0; + uint16_t pval = SFR_DATA_U16; + + + // PHY Initialization: REG_WRITE(0x2f8, 0, 0, pval >> 8, pval); @@ -83,9 +84,8 @@ void rtl8224_phy_enable(void) __banked phy_write_mask(0x1, 0x1e, 0xa90, pval); phy_read(0, 0x1e, 0xa90); - pval = SFR_DATA_8; - pval <<= 8; - pval |= SFR_DATA_0; + pval = SFR_DATA_U16; + delay(50); print_string("\r\nrtl8224_phy_enable done\r\n"); @@ -102,44 +102,34 @@ void phy_config(uint8_t phy) __banked // PHY configuration: External 8221B? // p081e.75f3:ffff P000100.1e0075f3:fffe phy_read(phy, 0x1e, 0x75f3); - pval = SFR_DATA_8; - pval <<= 8; - pval |= SFR_DATA_0 & 0xfe; + pval = SFR_DATA_U16 & 0xfffe; phy_write(phy, 0x1e, 0x75f3, pval); delay(20); // p081e.697a:ffff P000100.1e00697a:ffc1 / p031e.697a:0003 P000008.1e00697a:0001 // SERDES OPTION 1 Register (MMD 30.0x6) bits 0-5: 0x01: Set HiSGMII+SGMII phy_read(phy, 0x1e, 0x697a); - pval = SFR_DATA_8; - pval <<= 8; - pval |= SFR_DATA_0 & 0xc0 | 0x01; + pval = SFR_DATA_U16 & 0xffc0 | 0x0001; phy_write(phy, 0x1e, 0x697a, pval); delay(20); // p031f.a432:0811 P000008.1f00a432:0831 // PHYCR2 PHY Specific Control Register 2, MMD 31. 0xA432), set bit 5: enable EEE phy_read(phy, 0x1f, 0xa432); - pval = SFR_DATA_8; - pval <<= 8; - pval |= SFR_DATA_0 | 0x20; + pval = SFR_DATA_U16 | 0x0021; phy_write(phy, 0x1f, 0xa432, pval); // p0307.003e:0000 P000008.0700003e:0001 // EEE avertisment 2 register MMMD 7.0x003e, set bit 0: 2.5G has EEE capability phy_read(phy, 0x7, 0x3e); - pval = SFR_DATA_8; - pval <<= 8; - pval |= SFR_DATA_0 | 0x1; + pval = SFR_DATA_U16 | 0x0001; phy_write(phy, 0x7, 0x3e, pval); delay(20); // p031f.a442:043c P000008.1f00a442:0430 // Unknown, but clear bits 2/3 phy_read(phy, 0x1f, 0xa442); - pval = SFR_DATA_8; - pval <<= 8; - pval |= SFR_DATA_0 & 0xf3; + pval = SFR_DATA_U16 & 0x00f3; phy_write(phy, 0x1f, 0xa442, pval); delay(20); @@ -150,18 +140,14 @@ void phy_config(uint8_t phy) __banked // p031e.75b2:0000 P000008.1e0075b2:0060 // set bits 5/6 phy_read(phy, 0x1e, 0x75b2); - pval = SFR_DATA_8; - pval <<= 8; - pval |= SFR_DATA_0 | 0x60; + pval = SFR_DATA_U16 | 0x0060; phy_write(phy, 0x1e, 0x75b2, pval); delay(20); // p081f.d040:ffff P000100.1f00d040:feff // LCR6 (LED Control Register 6, MMD 31.D040), set bits 8/9 to 0b10 phy_read(phy, 0x1e, 0xd040); - pval = (SFR_DATA_8 & 0xfc) | 0x02; - pval <<= 8; - pval |= SFR_DATA_0; + pval = SFR_DATA_U16 & 0xfc00 | 0x0002; phy_write(phy, 0x1e, 0xd040, pval); delay(20); @@ -171,16 +157,13 @@ void phy_config(uint8_t phy) __banked // Set bit 14, sleep, then clear again, according to the datasheet these bits are reserved phy_read(phy, 0x1f, 0xa400); - pval = SFR_DATA_8 | 0x40; - pval <<= 8; - pval |= SFR_DATA_0; + + pval = SFR_DATA_U16 | 0x4000; phy_write(phy, 0x1f, 0xa400, pval); delay(20); phy_read(phy, 0x1f, 0xa400); - pval = SFR_DATA_8 & 0xbf; - pval <<= 8; - pval |= SFR_DATA_0; + pval = SFR_DATA_U16 & 0xbfff; phy_write(phy, 0x1f, 0xa400, pval); delay(20); @@ -195,9 +178,9 @@ void phy_config_8224(void) __banked uint16_t pval; print_string("\r\nphy_config_8224 called\r\n"); phy_read(0, 0x1e, 0x7b20); - pval = SFR_DATA_8; - pval <<= 8; - pval |= SFR_DATA_0; + pval = SFR_DATA_U16; + + REG_WRITE(0x2f8, 0, 0, pval >> 8, pval); pval &= 0x0fe0; @@ -228,7 +211,7 @@ void phy_set_mode(uint8_t port, uint8_t speed, uint8_t flow_control, uint8_t dup { uint16_t v; phy_read(port, 0x1f, 0xa610); - v = (((uint16_t)SFR_DATA_8) << 8) | SFR_DATA_0; + v = SFR_DATA_U16; if (speed == PHY_OFF) { phy_write(port, 0x1f, 0xa610, v | 0x0800); return; @@ -253,14 +236,14 @@ void phy_set_mode(uint8_t port, uint8_t speed, uint8_t flow_control, uint8_t dup phy_write(port, 0x07, 0x20, 0x6001); // bit 14: SLAVE, bit 13: Multi-Port device, 1: LD Loop timin enableed // GBCR (1000Base-T Control Register, MMD 31.0xA412) phy_read(port, 0x1f, 0xa412); - v = (((uint16_t)SFR_DATA_8) << 8) | SFR_DATA_0; + v = SFR_DATA_U16; phy_write(port, 0x1f, 0xa412, v | 0x0200); } else if (speed == PHY_SPEED_2G5) { // Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020) phy_write(port, 0x07, 0x20, 0x6081); // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD Loop timin enableed // GBCR (1000Base-T Control Register, MMD 31.0xA412) phy_read(port, 0x1f, 0xa412); - v = (((uint16_t)SFR_DATA_8) << 8) | SFR_DATA_0; + v = SFR_DATA_U16; phy_write(port, 0x1f, 0xa412, v & 0xfdff); } phy_write(port, 0x07, 0x00, 0x3200); // Enable AN