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update vlan.md
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@@ -33,8 +33,8 @@ An entry is deleted by adding an invalid entry (00 instead of 0x02 in
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RTL837x_TBL_DATA_IN_A).
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RTL837x_TBL_DATA_IN_A).
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A port is assigned a PVID by setting the PVID-bits of the corresponding
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A port is assigned a PVID by setting the PVID-bits of the corresponding
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register of the port. 2 ports share a register. One port uses the higher
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register of the port. 2 ports share a register. An odd port uses bits [23:12],
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16 bits, the other (even ports) use the lower. The base register is
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an even port uses bits [11:0]. The base register is
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RTL837x_PVID_BASE_REG (0x4e1c) and the registers go to 0x4e2c so that also
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RTL837x_PVID_BASE_REG (0x4e1c) and the registers go to 0x4e2c so that also
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the CPU-Port may have a PVID.
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the CPU-Port may have a PVID.
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@@ -51,7 +51,9 @@ registers 0x1238, 0x1338, ...
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The code currently provides the following functions:
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The code currently provides the following functions:
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```
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```
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void port_pvid_set(uint8_t port, __xdata uint16_t pvid) __banked;
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void port_pvid_set(uint8_t port, __xdata uint16_t pvid) __banked;
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void vlan_create(uint16_t vlan, uint16_t members, uint16_t tagged) __banked;
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uint16_t port_pvid_get(uint8_t port) __banked;
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void vlan_create(void) __banked; // reads from global vlan_settings
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int8_t vlan_get(register uint16_t vlan) __banked; // returns data in sfr_data
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void vlan_delete(uint16_t vlan) __banked;
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void vlan_delete(uint16_t vlan) __banked;
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```
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```
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