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https://github.com/logicog/RTLPlayground.git
synced 2026-10-29 17:54:14 +08:00
fix: initialize CPU MAC9 VLAN state independently of user port count
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4 files changed
+48
-5
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@@ -271,7 +271,7 @@ void vlan_setup(void) __banked
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wait_table_ready();
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wait_table_ready();
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// Set PVID 1 for every port. TODO: Skip unused ports!
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// Set PVID 1 for every port. TODO: Skip unused ports!
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for (uint8_t i = machine.min_port; i <= machine.max_port + 1; i++) { // Do this also for the CPU port (+1)
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for (uint8_t i = machine.min_port; i <= CPU_PORT; i++) { // CPU MAC is independent of the last user port
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uint16_t reg = RTL837x_PVID_BASE_REG + ((i >> 1) << 2);
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uint16_t reg = RTL837x_PVID_BASE_REG + ((i >> 1) << 2);
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#ifdef DEBUG
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#ifdef DEBUG
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print_byte(i); write_char(':'); write_char(' '); print_short(reg); write_char('=');
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print_byte(i); write_char(':'); write_char(' '); print_short(reg); write_char('=');
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@@ -307,7 +307,7 @@ void vlan_setup(void) __banked
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REG_SET(RTL837X_VLAN_L2_LRN_DIS_0, 0);
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REG_SET(RTL837X_VLAN_L2_LRN_DIS_0, 0);
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REG_SET(RTL837X_VLAN_L2_LRN_DIS_1, 0);
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REG_SET(RTL837X_VLAN_L2_LRN_DIS_1, 0);
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// Enable VLAN 1: Ports 0-9, i.e. including the CPU port are untagged members
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// Enable VLAN 1: user ports untagged, CPU MAC9 tagged (untag bit 19 clear)
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REG_SET(RTL837x_TBL_DATA_IN_A, machine_detected.isRTL8373? 0x0207ffff : 0x0207e3f8); // 02: Entry valid, 7...: membership
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REG_SET(RTL837x_TBL_DATA_IN_A, machine_detected.isRTL8373? 0x0207ffff : 0x0207e3f8); // 02: Entry valid, 7...: membership
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REG_SET(RTL837X_TBL_CTRL, 0x00010303); // Write VLAN 1
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REG_SET(RTL837X_TBL_CTRL, 0x00010303); // Write VLAN 1
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@@ -0,0 +1,10 @@
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# Invoke: make -C test -f Makefile -f cpu_vlan.mk run-cpu-vlan
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CPU_TESTS=build/test_cpu_vlan_full build/test_cpu_vlan_restricted build/test_cpu_vlan_8372
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build/test_cpu_vlan_full: test_cpu_vlan.c $(TABLE_ENV) | build
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$(CC) $(CFLAGS) -no-pie $(filter %.c,$^) -o $@ $(LDFLAGS)
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build/test_cpu_vlan_restricted: test_cpu_vlan.c $(TABLE_ENV) | build
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$(CC) $(CFLAGS) -no-pie -DRTLP_TEST_MAX_PORT=7 $(filter %.c,$^) -o $@ $(LDFLAGS)
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build/test_cpu_vlan_8372: test_cpu_vlan.c $(TABLE_ENV) | build
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$(CC) $(CFLAGS) -no-pie -DRTLP_TEST_MAX_PORT=7 -DRTLP_TEST_MIN_PORT=3 -DRTLP_TEST_IS8373=0 $(filter %.c,$^) -o $@ $(LDFLAGS)
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run-cpu-vlan: $(CPU_TESTS)
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@for t in $(CPU_TESTS); do $$t || exit 1; done
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+12
-3
@@ -56,15 +56,24 @@ const uint8_t hex_chars[] = "0123456789abcdef";
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uint8_t *hex = (uint8_t *)hex_chars;
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uint8_t *hex = (uint8_t *)hex_chars;
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/* ---- a 9-port RTL8373 whose logical ports map to themselves ---- */
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/* ---- a 9-port RTL8373 whose logical ports map to themselves ---- */
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#ifndef RTLP_TEST_MAX_PORT
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#define RTLP_TEST_MAX_PORT 8
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#endif
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#ifndef RTLP_TEST_MIN_PORT
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#define RTLP_TEST_MIN_PORT 0
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#endif
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#ifndef RTLP_TEST_IS8373
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#define RTLP_TEST_IS8373 1
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#endif
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const struct machine machine = {
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const struct machine machine = {
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.machine_name = "HOSTTEST",
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.machine_name = "HOSTTEST",
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.min_port = 0,
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.min_port = RTLP_TEST_MIN_PORT,
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.max_port = 8,
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.max_port = RTLP_TEST_MAX_PORT,
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.n_sfp = 0,
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.n_sfp = 0,
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.log_to_phys_port = { 1, 2, 3, 4, 5, 6, 7, 8, 9 },
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.log_to_phys_port = { 1, 2, 3, 4, 5, 6, 7, 8, 9 },
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.phys_to_log_port = { 0, 1, 2, 3, 4, 5, 6, 7, 8 },
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.phys_to_log_port = { 0, 1, 2, 3, 4, 5, 6, 7, 8 },
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};
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};
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struct machine_runtime machine_detected = { .isRTL8373 = 1 };
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struct machine_runtime machine_detected = { .isRTL8373 = RTLP_TEST_IS8373 };
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/* ---- firmware state the modules read or write ---- */
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/* ---- firmware state the modules read or write ---- */
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uint8_t outbuf[TCP_OUTBUF_SIZE];
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uint8_t outbuf[TCP_OUTBUF_SIZE];
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@@ -0,0 +1,24 @@
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#include <stdint.h>
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#include <stdio.h>
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#include "rtl837x_common.h"
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#include "rtl837x_port.h"
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#include "machine.h"
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#include "support.h"
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#include "hw_mock.h"
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extern const struct machine machine;
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extern struct machine_runtime machine_detected;
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int main(void) {
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hw_reset();out_reset();
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hw_reg_set(RTL837X_VLAN_PORT_EGR_TAG,0xa50fffff);
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hw_reg_set(RTL837x_PVID_BASE_REG+16,0x5a123456);
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vlan_setup();
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uint32_t untouched=(1u<<(machine.min_port*2))-1;
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CHECK(hw_reg_get(RTL837X_VLAN_PORT_EGR_TAG)==(0xa5000000|untouched),"CPU egress set, unrelated bits preserved");
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CHECK(hw_reg_get(RTL837x_PVID_BASE_REG+16)==0x5a001001,"CPU PVID initialized explicitly");
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uint16_t active=((1u<<(machine.max_port+1))-1)&~((1u<<machine.min_port)-1);
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CHECK(hw_reg_get(RTL837X_VLAN_PORT_IGR_FLTR)==(active|PMASK_CPU),"CPU ingress included, excluded user ports rejected");
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CHECK(hw_vlan_word(1)==(machine_detected.isRTL8373?0x0207ffff:0x0207e3f8),"existing family VLAN membership preserved");
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CHECK(hw_vlan_word(2)==0,"no unrelated VLAN changed");
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printf("CPU VLAN min=%u max=%u RTL8373=%u: %d checks, %d failed\n",machine.min_port,machine.max_port,machine_detected.isRTL8373,tests_run,tests_failed);
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return tests_failed?1:0;
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}
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