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fix-link-speed

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This commit is contained in:
chriz
2026-02-10 23:17:04 +01:00
parent 0099c2a03a
commit 859a50bd82
3 changed files with 42 additions and 12 deletions
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httpd/page_impl.c
+18 -6
View File
@@ -626,13 +626,25 @@ void send_status(void)
} }
slen += strtox(outbuf + slen, ",\"link\":"); slen += strtox(outbuf + slen, ",\"link\":");
if (i < 8) uint8_t b = 0;
reg_read_m(RTL837X_REG_LINKS); // Determine link state
reg_read_m(RTL837X_REG_LINKS_STS);
if(!((sfr_data[(i / 8) + 1] >> (i % 8 ) & 1)))
{
b = 0; //link down
}
else else
reg_read_m(RTL837X_REG_LINKS_89); {
uint8_t b = sfr_data[3 - ((i & 7) >> 1)]; //Determine link speed
b = (i & 1) ? b >> 4 : b & 0xf; if (i < 8)
reg_read_m(RTL837X_REG_LINKS);
else
reg_read_m(RTL837X_REG_LINKS_89);
b = sfr_data[3 - ((i & 7) >> 1)];
b = ((i & 1) ? b >> 4 : b & 0xf) + 1;
}
char_to_html('0' + b); char_to_html('0' + b);
STAT_GET(STAT_COUNTER_TX_PKTS, i); STAT_GET(STAT_COUNTER_TX_PKTS, i);
rtl837x_port.c
+22 -6
View File
@@ -369,15 +369,28 @@ void port_stats_print(void) __banked
} }
} }
if (i < 8) uint8_t b = 0;
reg_read_m(RTL837X_REG_LINKS);
// Determine link state
reg_read_m(RTL837X_REG_LINKS_STS);
if(!((sfr_data[(i / 8) + 1] >> ( i % 8 ) & 1)))
{
b = 99;
}
else else
reg_read_m(RTL837X_REG_LINKS_89); {
uint8_t b = sfr_data[3 - ((i & 7) >> 1)]; if (i < 8)
b = (i & 1) ? b >> 4 : b & 0xf; reg_read_m(RTL837X_REG_LINKS);
else
reg_read_m(RTL837X_REG_LINKS_89);
b = sfr_data[3 - ((i & 7) >> 1)];
b = (i & 1) ? b >> 4 : b & 0xf;
}
switch (b) { switch (b) {
case 0: case 0:
print_string("Down\t"); print_string("10M\t");
break; break;
case 1: case 1:
print_string("100M\t"); print_string("100M\t");
@@ -391,6 +404,9 @@ void port_stats_print(void) __banked
case 5: case 5:
print_string("2.5G\t"); print_string("2.5G\t");
break; break;
case 99:
print_string("Down\t");
break;
default: default:
print_string("Up\t"); print_string("Up\t");
break; break;
rtl837x_regs.h
+2
View File
@@ -66,6 +66,8 @@
#define RTL837X_REG_LINKS 0x63f0 #define RTL837X_REG_LINKS 0x63f0
#define RTL837X_REG_LINKS_89 0x63f4 #define RTL837X_REG_LINKS_89 0x63f4
#define RTL837X_REG_LINKS_STS 0x63E8
/* Each nibble encodes the link state of a port. /* Each nibble encodes the link state of a port.
Port 0 appears to be the CPU port Port 0 appears to be the CPU port
The RTL8372 serves ports 4-7, port 3 is the RTL8221 The RTL8372 serves ports 4-7, port 3 is the RTL8221