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logicog committed 2025-06-05 20:13:07 +02:00
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@@ -64,7 +64,7 @@ Overlay 1 Overlay 2 Overlay n
--------- 0xffff --------- -------- 0xffff -------- -------- 0xffff --------- 0xffff --------- -------- 0xffff -------- -------- 0xffff
``` ```
The RTL837x firmware images are organized as follows: The RTL837x firmware images are organized as follows:
The first 2 bytes of the image give the size of the prefetched data at the The first 2 bytes of the image give the size of the prefetched data at the
start of the CPU power up. The default is 0x4000 (bytes: 0x00 0x40), which start of the CPU power up. The default is 0x4000 (bytes: 0x00 0x40), which
means that the entire shared area of the code memory in all banks, means that the entire shared area of the code memory in all banks,