From 74fbec10446e1ea33c712af10b175c2f650914e6 Mon Sep 17 00:00:00 2001
From: logicog <git@logicog.de>
Date: Tue, 19 Aug 2025 09:31:32 +0200
Subject: [PATCH] Add logical to physical mapping of ports on RTL8372

---
 rtl837x_port.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/rtl837x_port.c b/rtl837x_port.c
index c44b76c..2c3e17d 100644
--- a/rtl837x_port.c
+++ b/rtl837x_port.c
@@ -25,6 +25,11 @@ extern __xdata uint8_t isRTL8373;
 
 __xdata	uint32_t l2_head;
 
+// The mapping of logical to physical ports on the RTL8372
+// Port 6 is always an SFP+ port. Port 5 may be RTL8221 or SFP+
+__code uint8_t log_to_phys_port[9] = {
+	0, 0, 0, 5, 1, 2, 3, 4, 6
+};
 
 void port_mirror_set(register uint8_t port, __xdata uint16_t rx_pmask, __xdata uint16_t tx_pmask) __banked
 {