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gpio: SOC only has 64 gpio not 96.

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Remove BANK_A
Rename BANK_B to GPIO_00_31
Rename BACK_C to GPIO_32_63

Added also _INPUT, _DIRECTIOn registers
This commit is contained in:
René van Dorst
2025-09-06 17:04:25 +02:00
parent 8e9cababfb
commit 74b8280d80
4 changed files with 32 additions and 27 deletions
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rtlplayground.c
+18 -18
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@@ -873,7 +873,7 @@ void sfp_print_info(uint8_t sfp)
void handle_sfp(void)
{
reg_read_m(RTL837X_REG_GPIO_B);
reg_read_m(RTL837X_REG_GPIO_00_31_INPUT);
if ((sfp_pins_last & 0x1) && (!(sfr_data[0] & 0x40))) {
sfp_pins_last &= ~0x01;
print_string("\n<MODULE INSERTED> ");
@@ -893,7 +893,7 @@ void handle_sfp(void)
print_string("\n<MODULE REMOVED>\n");
}
reg_read_m(RTL837X_REG_GPIO_C);
reg_read_m(RTL837X_REG_GPIO_32_63_INPUT);
if ((sfp_pins_last & 0x2) && (!(sfr_data[3] & 0x20))) {
sfp_pins_last &= ~0x02;
print_string("\n<SFP-RX OK>\n");
@@ -903,7 +903,7 @@ void handle_sfp(void)
print_string("\n<SFP-RX LOS>\n");
}
reg_read_m(RTL837X_REG_GPIO_C);
reg_read_m(RTL837X_REG_GPIO_32_63_INPUT);
if ((sfp_pins_last & 0x10) && (!(sfr_data[1] & 0x04))) {
sfp_pins_last &= ~0x10;
print_string("\n<MODULE 2 INSERTED> ");
@@ -989,7 +989,7 @@ void idle(void)
handle_sfp();
/* Button pressed on KL-8xhm-x2:
reg_read(RTL837X_REG_GPIO_C);
reg_read(RTL837X_REG_GPIO_32_63_INPUT);
if (!(sfr_data[2] & 0x40))
print_string("Button pressed\n");
*/
@@ -1038,12 +1038,12 @@ void setup_external_irqs(void)
void rtl8224_enable(void)
{
// Set Pin 4 low
reg_bit_clear(RTL837X_REG_GPIO_A, 4);
reg_bit_clear(RTL837X_REG_GPIO_32_63_OUTPUT, 4);
// Configure Pin as output
reg_bit_set(RTL837X_REG_GPIO_CONF_A, 4);
reg_bit_set(RTL837X_REG_GPIO_32_63_DIRECTION, 4);
delay(100);
// Set pin 4 high
reg_bit_set(RTL837X_REG_GPIO_A, 4);
reg_bit_set(RTL837X_REG_GPIO_32_63_OUTPUT, 4);
delay(500);
}
@@ -1064,9 +1064,9 @@ void setup_clock(void)
reg_write_m(RTL837X_REG_HW_CONF);
// Enable serial interface, set bit 0
reg_read_m(RTL837X_PIN_MUX_B);
reg_read_m(RTL837X_PIN_MUX_1);
sfr_mask_data(0, 0x1, 0x1);
reg_write_m(RTL837X_PIN_MUX_B);
reg_write_m(RTL837X_PIN_MUX_1);
}
@@ -1286,7 +1286,7 @@ void led_config_9xh(void)
reg_bit_clear(0x65dc, 0x1b);
// r7f8c:30000000 R7f8c-30000000 r7f8c:30000000 R7f8c-38000000
reg_bit_set(RTL837X_PIN_MUX_A, 0x1b);
reg_bit_set(RTL837X_PIN_MUX_0, 0x1b);
// R6548-0041017f
REG_SET(0x6548, 0x0041017f);
@@ -1338,13 +1338,13 @@ void led_config(void)
// Set bits 1b/1d of 0x7f8c: r7f8c:30000000 R7f8c-30000000 r7f8c:30000000 R7f8c-38000000
if (nSFPPorts == 2) {
reg_bit_set(RTL837X_PIN_MUX_A, 0x1b); // R7f8c-28000000
reg_bit_clear(RTL837X_PIN_MUX_A, 0x1c); // R7f8c-28000000
reg_bit_set(RTL837X_PIN_MUX_A, 0x1d); // R7f8c-28000000
reg_bit_set(RTL837X_PIN_MUX_0, 0x1b); // R7f8c-28000000
reg_bit_clear(RTL837X_PIN_MUX_0, 0x1c); // R7f8c-28000000
reg_bit_set(RTL837X_PIN_MUX_0, 0x1d); // R7f8c-28000000
} else {
reg_bit_set(RTL837X_PIN_MUX_A, 0x1d);
reg_bit_set(RTL837X_PIN_MUX_A, 0x1c);
reg_bit_set(RTL837X_PIN_MUX_A, 0x1b);
reg_bit_set(RTL837X_PIN_MUX_0, 0x1d);
reg_bit_set(RTL837X_PIN_MUX_0, 0x1c);
reg_bit_set(RTL837X_PIN_MUX_0, 0x1b);
}
// LED setup
// r6520:0021fdb0 R6520-0021e7b0 r6520:0021e7b0 R6520-0021e6b0 r65f8:00000018 R65f8-00000018 R65fc-fffff000 r6600:00000000 R6600-0000000f r65dc:5fffff00 R65dc-7fffff00 r65dc:7fffff00 R65dc-77ffff00
@@ -1620,10 +1620,10 @@ void setup_i2c(void)
REG_SET(0x041c, 0);
// HW Control register, enable I2C?
reg_read_m(RTL837X_PIN_MUX_B);
reg_read_m(RTL837X_PIN_MUX_1);
sfr_mask_data(3, 0x20, 0x00); // Clear bit 29
sfr_mask_data(0, 0x60, 0x40); // Set bits 5-6 to 0b10
reg_write_m(RTL837X_PIN_MUX_B);
reg_write_m(RTL837X_PIN_MUX_1);
}