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Add banking support

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This commit is contained in:
logicog
2025-06-25 13:20:06 +02:00
parent f543b58490
commit 73a0a7d137
6 changed files with 69 additions and 96 deletions
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Makefile
+4 -2
View File
@@ -23,7 +23,7 @@ clean:
# mv -f $(addprefix $(basename $^), .lst .rel .sym) .
rtlplayground.ihx: crtstart.rel $(OBJS)
$(CC) $(CC_FLAGS) -Wl-bHOME=${BOOTLOADER_ADDRESS} -o $@ $^
$(CC) $(CC_FLAGS) -Wl-bHOME=${BOOTLOADER_ADDRESS} -Wl-bBANK1=0x14000 -Wl-r -o $@ $^
%.img: %.ihx
objcopy --input-target=ihex -O binary $< $@
@@ -32,9 +32,11 @@ rtlplayground.ihx: crtstart.rel $(OBJS)
if [ -e $@ ]; then rm $@; fi
echo "0000000: 00 40" | xxd -r - $@
cat $< >> $@
truncate --size=16K $@
dd if=$< skip=80 bs=1024 >>$@
injector: injector.c
gcc $^ -o $@
.PHONY: clean all
.PRECIOUS: %.rel %.ihx
.PRECIOUS: %.rel %.ihx .img
rtl837x_flash.c
+11 -8
View File
@@ -9,6 +9,7 @@
__xdata uint8_t dio_enabled;
#pragma codeseg BANK1
/*
* Configure Memory Managed IO
@@ -36,8 +37,9 @@ void flash_configure_mmio(void)
* This configures uses fast single IO at 20.8 MHz when the CPU clock is at 20.8MHz
* and 62.5MHz when the CPU clock is configured at 125MHz
*/
void flash_init(uint8_t enable_dio)
void flash_init(uint8_t enable_dio) __banked
{
print_string("\r\n flash_init called\r\n");
if (enable_dio) {
// Configure fast DIO via divider/DIO/SIOconfig = 4 and read-cmd being 0xbb (for mmio)
SFR_FLASH_CONFIG = 9; // There may be a chip-select in here
@@ -63,6 +65,7 @@ void flash_init(uint8_t enable_dio)
dio_enabled = enable_dio;
flash_configure_mmio();
print_string("\r\n flash_init done");
}
uint8_t flash_read_status(void)
@@ -82,7 +85,7 @@ uint8_t flash_read_status(void)
}
void flash_read_uid(void)
void flash_read_uid(void) __banked
{
while (flash_read_status() & 0x1);
@@ -118,7 +121,7 @@ void flash_read_uid(void)
}
void flash_read_jedecid(void)
void flash_read_jedecid(void) __banked
{
while (flash_read_status() & 0x1);
@@ -145,7 +148,7 @@ void flash_read_jedecid(void)
}
void flash_write_enable(void)
void flash_write_enable(void) __banked
{
short status;
@@ -170,7 +173,7 @@ void flash_write_enable(void)
}
void flash_dump(uint32_t addr, uint8_t len)
void flash_dump(uint32_t addr, uint8_t len) __banked
{
short status;
do {
@@ -215,7 +218,7 @@ void flash_dump(uint32_t addr, uint8_t len)
}
void flash_read_security(uint32_t addr, uint8_t len)
void flash_read_security(uint32_t addr, uint8_t len) __banked
{
while (flash_read_status() & 0x1);
@@ -251,7 +254,7 @@ void flash_read_security(uint32_t addr, uint8_t len)
}
void flash_block_erase(uint32_t addr)
void flash_block_erase(uint32_t addr) __banked
{
flash_write_enable();
SFR_FLASH_TCONF = 8;
@@ -269,7 +272,7 @@ void flash_block_erase(uint32_t addr)
}
void flash_write_bytes(uint32_t addr, __xdata uint8_t *ptr, uint8_t len)
void flash_write_bytes(uint32_t addr, __xdata uint8_t *ptr, uint8_t len) __banked
{
uint8_t exit_loop = 0;
rtl837x_flash.h
+8 -9
View File
@@ -2,13 +2,12 @@
#define _RTL837X_FLASH_H_
#include <stdint.h>
uint8_t flash_read_status(void);
void flash_init(uint8_t enable_dio);
void flash_read_uid(void);
void flash_write_enable(void);
void flash_dump(uint32_t addr, uint8_t len);
void flash_read_jedecid(void);
void flash_read_security(uint32_t addr, uint8_t len);
void flash_block_erase(uint32_t addr);
void flash_write_bytes(uint32_t addr, __xdata uint8_t *ptr, uint8_t len);
void flash_init(uint8_t enable_dio)__banked ;
void flash_read_uid(void) __banked;
void flash_write_enable(void)__banked ;
void flash_dump(uint32_t addr, uint8_t len) __banked;
void flash_read_jedecid(void) __banked;
void flash_read_security(uint32_t addr, uint8_t len)__banked ;
void flash_block_erase(uint32_t addr) __banked;
void flash_write_bytes(uint32_t addr, __xdata uint8_t *ptr, uint8_t len)__banked ;
#endif
rtl837x_regs.h
+29 -5
View File
@@ -55,11 +55,35 @@
#define RTL837X_REG_RX_RINGPTR 0x787c
#define RTL837X_REG_RX_DONE 0x784c
#define REG_SET(r, v) SFR_DATA_24 = (v >> 24) & 0xff; \
SFR_DATA_16 = (v >> 16) & 0xff; \
SFR_DATA_8 = (v >> 8 & 0xff); \
SFR_DATA_0 = v & 0xff; \
/*
#define REG_SET(r, v) SFR_DATA_24 = ((v) >> 24) & 0xff; \
SFR_DATA_16 = ((v) >> 16) & 0xff; \
SFR_DATA_8 = ((v) >> 8 & 0xff); \
SFR_DATA_0 = (v) & 0xff; \
reg_write(r);
#define REG_WRITE(r, v24, v16, v8, v0) SFR_DATA_24 = (v24); \
SFR_DATA_16 = (v16); \
SFR_DATA_8 = (v8); \
SFR_DATA_0 = (v0); \
reg_write(r);
*/
#define REG_SET(r, v) SFR_DATA_24 = ((v) >> 24) & 0xff; \
SFR_DATA_16 = ((v) >> 16) & 0xff; \
SFR_DATA_8 = ((v) >> 8 & 0xff); \
SFR_DATA_0 = (v) & 0xff; \
reg_write(r); \
write_char('R'); print_short(r); write_char(':'); \
print_byte(((v) >> 24) & 0xff); print_byte((v) >> 16 & 0xff); print_byte((v) >> 8 & 0xff); print_byte( (v) & 0xff);
#define REG_WRITE(r, v24, v16, v8, v0) SFR_DATA_24 = (v24); \
SFR_DATA_16 = (v16); \
SFR_DATA_8 = (v8); \
SFR_DATA_0 = (v0); \
reg_write(r);
/* \
write_char('R'); print_short(r); write_char(':'); print_byte(v24); print_byte(v16); print_byte(v8); print_byte(v0);
*/
#endif
rtl837x_sfr.h
+2 -1
View File
@@ -41,7 +41,8 @@ __sfr __at(0xca) RCAP2L;
__sfr __at(0xcb) RCAP2H;
/* SFR Bank control register: 0x0-3f. A value of 0 is bank 1 */
__sfr __at(0x96) SFR_BANK;
__sfr __at(0x96) PSBANK;
__sfr __at(0x96) SFR_BANK_RET;
__sfr __at(0x8e) CKCON;
rtlplayground.c
+15 -71
View File
@@ -410,22 +410,15 @@ void nic_rx_packet(uint16_t buffer, uint16_t ring_ptr)
void nic_tx_packet(uint16_t ring_ptr)
{
uint16_t buffer = (uint16_t) tx_buf;
print_string(", xmem: ");
print_short((uint16_t)buffer);
SFR_NIC_DATA_H = buffer >> 8;
SFR_NIC_DATA_L = buffer;
print_string("R"); print_short(buffer);
ring_ptr <<= 3;
ring_ptr |= 0x8000;
SFR_NIC_RING_L = ring_ptr;
SFR_NIC_RING_H = ring_ptr >> 8;
print_string(":"); print_short(ring_ptr);
uint16_t len =(((uint16_t)tx_buf[5]) << 8) | tx_buf[4];
len += 0xf;
len >>= 3;
print_string("-");
print_short(len);
print_string(" ");
SFR_NIC_CTRL = len;
do { } while (SFR_NIC_CTRL != 0);
}
@@ -440,11 +433,11 @@ void nic_tx_packet(uint16_t ring_ptr)
uint8_t read_flash(uint8_t bank, __code uint8_t *addr)
{
uint8_t v;
uint8_t current_bank = SFR_BANK;
uint8_t current_bank = PSBANK;
SFR_BANK = bank;
PSBANK = bank;
v = *addr;
SFR_BANK = current_bank;
PSBANK = current_bank;
return v;
}
@@ -729,9 +722,7 @@ uint8_t sfp_read_reg(uint8_t reg)
sfr_mask_data(1, 0xf0, 0x70);
reg_write_m(0x0418);
SFR_DATA_24 = SFR_DATA_16 = SFR_DATA_8 = 0;
SFR_DATA_0 = reg;
reg_write(0x0420);
REG_WRITE(0x0420, 0, 0, 0, reg);
// Execute I2C Read
reg_bit_set(0x418, 0);
@@ -981,25 +972,14 @@ void sleep(uint16_t t)
void reset_chip(void)
{
SFR_DATA_24 = 0x00;
SFR_DATA_16 = 0x00;
SFR_DATA_8 = 0x00;
SFR_DATA_0 = 0x01;
reg_write(RTL837X_REG_RESET);
REG_SET(RTL837X_REG_RESET, 1);
}
void setup_external_irqs(void)
{
SFR_DATA_24 = 0x00;
SFR_DATA_16 = 0x00;
SFR_DATA_8 = 0x00;
SFR_DATA_0 = 0x42;
reg_write(0x5f84);
SFR_DATA_8 = 0x03;
SFR_DATA_0 = 0xff;
reg_write(0x5f34);
REG_SET(0x5f84, 0x42);
REG_SET(0x5f34, 0x3ff);
EX0 = 1; // Enable external IRQ 0
IT0 = 1; // External IRQ on falling edge
@@ -1097,11 +1077,7 @@ void rtl8224_phy_enable(void)
print_string("\r\n");
// PHY Initialization:
SFR_DATA_24 = 0;
SFR_DATA_16 = 0;
SFR_DATA_8 = pval >> 8;
SFR_DATA_0 = pval;
reg_write(0x2f8);
REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
print_string("\r\nA Reg 0x2f8: ");
print_reg(0x2f8);
@@ -1109,11 +1085,7 @@ void rtl8224_phy_enable(void)
pval &= 0xfff0;
pval |= 0x0c;
SFR_DATA_24 = 0;
SFR_DATA_16 = 0;
SFR_DATA_8 = pval >> 8;
SFR_DATA_0 = pval;
reg_write(0x2f4);
REG_WRITE(0x2f4, 0, 0, pval >> 8, pval);
print_string("\r\nA Reg 0x2f4: ");
print_reg(0x2f4);
@@ -1241,11 +1213,7 @@ void sds_init(void)
print_string("\r\n");
// PHY Initialization:
SFR_DATA_24 = 0;
SFR_DATA_16 = 0;
SFR_DATA_8 = pval >> 8;
SFR_DATA_0 = pval;
reg_write(0x2f8);
REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
print_string("\r\nA Reg 0x2f8: ");
print_reg(0x2f8);
@@ -1253,11 +1221,7 @@ void sds_init(void)
pval &= 0xfff0;
pval |= 0x0a;
SFR_DATA_24 = 0;
SFR_DATA_16 = 0;
SFR_DATA_8 = pval >> 8;
SFR_DATA_0 = pval;
reg_write(0x2f4);
REG_WRITE(0x2f4, 0, 0, pval >> 8, pval);
print_string("\r\nA Reg 0x2f4: ");
print_reg(0x2f4);
@@ -1272,22 +1236,14 @@ void sds_init(void)
print_string("\r\n");
// PHY Initialization:
SFR_DATA_24 = 0;
SFR_DATA_16 = 0;
SFR_DATA_8 = pval >> 8;
SFR_DATA_0 = pval;
reg_write(0x2f8);
REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
print_string("\r\nA Reg 0x2f8: ");
print_reg(0x2f8);
sleep(10);
pval &= 0xfff0;
SFR_DATA_24 = 0;
SFR_DATA_16 = 0;
SFR_DATA_8 = pval >> 8;
SFR_DATA_0 = pval;
reg_write(0x2f4);
REG_WRITE(0x2f4, 0, 0, pval >> 8, pval);
print_string("\r\nA Reg 0x2f4: ");
print_reg(0x2f4);
@@ -1330,21 +1286,13 @@ void phy_config_8224(void) {
sleep(20);
SFR_DATA_24 = 0;
SFR_DATA_16 = 0;
SFR_DATA_8 = pval >> 8;
SFR_DATA_0 = pval;
reg_write(0x2f8);
REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
print_string("\r\nA Reg 0x2f8: ");
print_reg(0x2f8);
sleep(20);
pval &= 0xfed;
SFR_DATA_24 = 0;
SFR_DATA_16 = 0;
SFR_DATA_8 = pval >> 8;
SFR_DATA_0 = pval;
reg_write(0x2f4);
REG_WRITE(0x2f4, 0, 0, pval >> 8, pval);
print_string("\r\nA Reg 0x2f4: ");
print_reg(0x2f4);
@@ -1963,8 +1911,6 @@ void bootloader(void)
print_string("\r\nStarting up...\r\n");
print_string(" Flash controller\r\n");
flash_init(0);
print_string(" > OK\r\n current status: ");
print_short(flash_read_status());
// The following will only show something else then 0xff if it was programmed for a managed switch
print_string("\r\n Testing read Securty Register 1\r\n");
@@ -1974,8 +1920,6 @@ void bootloader(void)
print_string("\r\n Testing read Securty Register 3\r\n");
flash_read_security(0x0003000, 40);
print_string(" > Flash status: ");
print_short(flash_read_status());
print_string("\r\n Dumping flash at 0x100\r\n");
flash_dump(0x100, 252);
rtl8372_init();