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https://github.com/logicog/RTLPlayground.git
synced 2026-10-29 17:54:14 +08:00
use macro for min_port and max_port for code optimization
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@@ -271,7 +271,7 @@ void vlan_setup(void) __banked
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wait_table_ready();
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// Set PVID 1 for every port. TODO: Skip unused ports!
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for (uint8_t i = machine.min_port; i <= machine.max_port + 1; i++) { // Do this also for the CPU port (+1)
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for (uint8_t i = MACHINE_MIN_PORT; i <= MACHINE_MAX_PORT + 1; i++) { // Do this also for the CPU port (+1)
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uint16_t reg = RTL837x_PVID_BASE_REG + ((i >> 1) << 2);
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#ifdef DEBUG
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print_byte(i); write_char(':'); write_char(' '); print_short(reg); write_char('=');
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@@ -459,7 +459,7 @@ void port_l2_setup(void) __banked
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port_l2_forget();
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for (uint8_t i = machine.min_port; i <= machine.max_port; i++) {
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for (uint8_t i = MACHINE_MIN_PORT; i <= MACHINE_MAX_PORT; i++) {
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// Limit the number of automatically learned MAC-Entries per port to 0x1040
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uint8_t idx = (i << 2);
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REG_SET(RTL837X_L2_LRN_PORT_CONSTRAINT + idx, 0x00001040);
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@@ -511,7 +511,7 @@ void port_media_show(uint8_t port) __banked
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void port_stats_print(void) __banked
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{
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print_string("\nPort\tState\tLink\tTxGood\t\tTxBad\t\tRxGood\t\tRxBad\t\tMACs\n");
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for (uint8_t i = machine.min_port; i <= machine.max_port; i++) {
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for (uint8_t i = MACHINE_MIN_PORT; i <= MACHINE_MAX_PORT; i++) {
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print_phys_port(i); write_char('\t');
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if (!machine.is_sfp[i]) {
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@@ -594,14 +594,14 @@ void port_stats_print(void) __banked
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void port_isolate(uint8_t port, __xdata uint16_t pmask) __banked
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{
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if (port <= machine.max_port)
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if (port <= MACHINE_MAX_PORT)
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REG_SET(RTL837X_PORT_ISOLATION_BASE + (port << 2), pmask);
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}
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uint16_t port_isolation_get(uint8_t port) __banked
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{
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if (port > machine.max_port)
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if (port > MACHINE_MAX_PORT)
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return 0;
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reg_read_m(RTL837X_PORT_ISOLATION_BASE + (port << 2));
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@@ -775,7 +775,7 @@ void port_eee_status(uint8_t port) __banked
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void port_eee_enable_all(__xdata uint8_t speed) __banked
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{
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for (uint8_t i = machine.min_port; i <= machine.max_port; i++) {
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for (uint8_t i = MACHINE_MIN_PORT; i <= MACHINE_MAX_PORT; i++) {
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if (i == 3 && machine.n_10g) {
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port_eee_enable(i, speed);
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} else if (i == 8 && machine.n_10g == 2) {
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@@ -792,7 +792,7 @@ void port_eee_enable_all(__xdata uint8_t speed) __banked
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void port_eee_disable_all(void) __banked
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{
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for (uint8_t i = machine.min_port; i <= machine.max_port; i++) {
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for (uint8_t i = MACHINE_MIN_PORT; i <= MACHINE_MAX_PORT; i++) {
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port_eee_disable(i);
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}
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}
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@@ -800,7 +800,7 @@ void port_eee_disable_all(void) __banked
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void port_eee_status_all(void) __banked
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{
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for (uint8_t i = machine.min_port; i <= machine.max_port; i++) {
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for (uint8_t i = MACHINE_MIN_PORT; i <= MACHINE_MAX_PORT; i++) {
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port_eee_status(i);
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}
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}
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@@ -908,7 +908,7 @@ void vlan_dump(void) __banked
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{
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print_string("Ingress VLAN configuration:\n");
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print_string("Port\tPVID\tType\tFiltering\n");
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for (uint8_t port = machine.min_port; port <= machine.max_port; port++) {
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for (uint8_t port = MACHINE_MIN_PORT; port <= MACHINE_MAX_PORT; port++) {
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print_vlan_ingress_port(port);
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}
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print_vlan_ingress_port(9);
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@@ -923,7 +923,7 @@ void vlan_dump(void) __banked
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/** Set the ingress VLAN filtering */
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bool port_ingress_vlan_filter_set(uint8_t port, __xdata bool enabled) __banked
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{
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if (port < machine.min_port || (port > machine.max_port && port != CPU_PORT)) {
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if (!MACHINE_PORT_VALID(port) && port != CPU_PORT) {
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return false;
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}
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if (enabled)
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@@ -937,7 +937,7 @@ bool port_ingress_vlan_filter_set(uint8_t port, __xdata bool enabled) __banked
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/** Get the ingress VLAN filtering status */
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bool port_ingress_vlan_filter_get(uint8_t port) __banked
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{
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if (port < machine.min_port || (port > machine.max_port && port != CPU_PORT)) {
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if (!MACHINE_PORT_VALID(port) && port != CPU_PORT) {
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return false;
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}
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