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Add speed bits for 5G/10G EEE

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logicog
2026-04-24 10:53:05 +02:00
parent c342964327
commit 6d579c4f00
1 changed files with 7 additions and 2 deletions
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phy.h
+7 -2
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@@ -22,16 +22,21 @@
#define PHY_ANEG_CTRL 0x00 #define PHY_ANEG_CTRL 0x00
#define PHY_ANEG_ADV 0x10 #define PHY_ANEG_ADV 0x10
#define PHY_ANEG_LP_ABILITY 0x13 #define PHY_ANEG_LP_ABILITY 0x13
#define PHY_ANEG_MGBASE_CTRL 0x20 #define PHY_ANEG_MGBASE_CTRL 0x20
#define PHY_ANEG_MGBASE_ADV 0x21 #define PHY_ANEG_MGBASE_ADV 0x21
#define PHY_EEE_ADV 0x3c #define PHY_EEE_ADV 0x3c
#define PHY_EEE_LP_ABILITY 0x3d #define PHY_EEE_LP_ABILITY 0x3d
#define PHY_EEE_ADV2 0x3e #define PHY_EEE_ADV2 0x3e
#define PHY_EEE_LP_ABILITY2 0x3f #define PHY_EEE_LP_ABILITY2 0x3f
// Register bits for EEE capabilities at a given speed // Register bits for EEE capabilities at a given speed
// PHY_EEE_ADV2
#define PHY_EEE_BIT_2G5 0x01 #define PHY_EEE_BIT_2G5 0x01
#define PHY_EEE_BIT_5G 0x02
// PHY_EEE_ADV
#define PHY_EEE_BIT_1G 0x04 #define PHY_EEE_BIT_1G 0x04
#define PHY_EEE_BIT_100M 0x02 #define PHY_EEE_BIT_100M 0x02
#define PHY_EEE_BIT_10G 0x08
/* /*
* MMD 31 Registers * MMD 31 Registers