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phy: fix whitespace and comments alinement

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This commit is contained in:
René van Dorst
2025-09-01 09:59:06 +02:00
committed by René van Dorst
parent d865862625
commit 689d208ff1
2 changed files with 9 additions and 24 deletions
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rtl837x_phy.c
-9
View File
@@ -71,9 +71,6 @@ void rtl8224_phy_enable(void) __banked
phy_read(0, 0x1e, 0xa90);
uint16_t pval = SFR_DATA_U16;
// PHY Initialization:
REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
@@ -86,7 +83,6 @@ void rtl8224_phy_enable(void) __banked
phy_read(0, 0x1e, 0xa90);
pval = SFR_DATA_U16;
delay(50);
print_string("\r\nrtl8224_phy_enable done\r\n");
}
@@ -155,9 +151,7 @@ void phy_config(uint8_t phy) __banked
// p031f.a400:1040 P000008.1f00a400:5040, then: p031f.a400:5040 P000008.1f00a400:1040
// FEDCR (Fast Ethernet Duplex Control Register, MMD 31.0xA400)
// Set bit 14, sleep, then clear again, according to the datasheet these bits are reserved
phy_read(phy, 0x1f, 0xa400);
pval = SFR_DATA_U16 | 0x4000;
phy_write(phy, 0x1f, 0xa400, pval);
delay(20);
@@ -179,9 +173,6 @@ void phy_config_8224(void) __banked
print_string("\r\nphy_config_8224 called\r\n");
phy_read(0, 0x1e, 0x7b20);
pval = SFR_DATA_U16;
REG_WRITE(0x2f8, 0, 0, pval >> 8, pval);
pval &= 0x0fe0;
pval |= 0x000d;
rtlplayground.c
-6
View File
@@ -1404,14 +1404,10 @@ void rtl8373_init(void)
// q000601:c800 Q000601:c804 q000601:c804 Q000601:c800
sds_read(0, 0x06, 0x01);
uint16_t pval = SFR_DATA_U16;
sds_write_v(0, 0x06, 0x01, pval | 0x04);
delay(50);
sds_read(0, 0x06, 0x01);
pval = SFR_DATA_U16;
sds_write_v(0, 0x06, 0x01, pval & 0xfffb);
phy_config_8224();
@@ -1427,8 +1423,6 @@ void rtl8373_init(void)
sds_read(1, 0x1f, 0x15);
pval = SFR_DATA_U16;
// r0a90:000000f3 R0a90-000000fc
reg_read_m(0xa90);
sfr_mask_data(0, 0x0f,0x0c);