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port, httpd: parenthesise the mixed operators and drop a dead local

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Compiling these two files for the host turns up warnings that SDCC does
not print: four places mix & with | and two mix && with ||, and l2_delete
keeps a counter it never reads. The parentheses only say what the
compiler already does, so the generated code is unchanged.

counter_to_html() reads the SFRs directly for the zero test, which saves
14 bytes of bank 1.
This commit is contained in:
d00f committed 2026-09-17 20:49:01 +02:00
1 parent d6253ddc25
commit 674dc1f35d
2 files changed
+7 -9
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httpd/page_impl.c
+1 -3
View File
@@ -180,7 +180,7 @@ void reg_to_html_long(uint16_t reg)
void counter_to_html(void) void counter_to_html(void)
{ {
reg_read_m(RTL837X_STAT_V_HIGH); reg_read_m(RTL837X_STAT_V_HIGH);
if (sfr_data[0] | sfr_data[1] | sfr_data[2] | sfr_data[3]) { if (SFR_DATA_24 | SFR_DATA_16 | SFR_DATA_8 | SFR_DATA_0) {
sfr_data_to_html(); sfr_data_to_html();
reg_to_html_long(RTL837X_STAT_V_LOW); reg_to_html_long(RTL837X_STAT_V_LOW);
} else { } else {
@@ -445,8 +445,6 @@ void l2_delete(uint16_t idx)
slen = strtox(outbuf, HTTP_RESPONCE_JSON); slen = strtox(outbuf, HTTP_RESPONCE_JSON);
dbg_string("L2 DELETE\n"); dbg_string("L2 DELETE\n");
dbg_short(idx); dbg_short(idx);
__xdata uint8_t entries_left = L2_MAX_TRANSFER;
do { do {
reg_read(RTL837X_TBL_CTRL); reg_read(RTL837X_TBL_CTRL);
} while (SFR_DATA_0 & TBL_EXECUTE); } while (SFR_DATA_0 & TBL_EXECUTE);
rtl837x_port.c
+6 -6
View File
@@ -102,9 +102,9 @@ static void port_pvid_write(uint8_t port, __xdata uint16_t pvid)
reg_read_m(reg); reg_read_m(reg);
if (port & 0x1) { if (port & 0x1) {
REG_WRITE(reg, sfr_data[0], pvid >> 4, sfr_data[2] & 0x0f | (pvid << 4), sfr_data[3]); REG_WRITE(reg, sfr_data[0], pvid >> 4, (sfr_data[2] & 0x0f) | (pvid << 4), sfr_data[3]);
} else { } else {
REG_WRITE(reg, sfr_data[0], sfr_data[1], sfr_data[2] & 0xf0 | (pvid >> 8), pvid); REG_WRITE(reg, sfr_data[0], sfr_data[1], (sfr_data[2] & 0xf0) | (pvid >> 8), pvid);
} }
} }
@@ -285,7 +285,7 @@ void vlan_setup(void) __banked
#endif #endif
reg_read_m(reg); reg_read_m(reg);
if (i & 0x1) { if (i & 0x1) {
REG_WRITE(reg, sfr_data[0], 0, sfr_data[2] & 0x0f | 0x10, sfr_data[3]); REG_WRITE(reg, sfr_data[0], 0, (sfr_data[2] & 0x0f) | 0x10, sfr_data[3]);
} else { } else {
REG_WRITE(reg, sfr_data[0], sfr_data[1], sfr_data[2] & 0xf0, 0x01); REG_WRITE(reg, sfr_data[0], sfr_data[1], sfr_data[2] & 0xf0, 0x01);
} }
@@ -758,7 +758,7 @@ void port_eee_enable_all(__xdata uint8_t speed) __banked
port_eee_enable(i, speed); port_eee_enable(i, speed);
} else { } else {
if (speed & EEE_10G) if (speed & EEE_10G)
port_eee_enable(i, speed & EEE_NORESET | EEE_2G5); port_eee_enable(i, (speed & EEE_NORESET) | EEE_2G5);
else else
port_eee_enable(i, speed); port_eee_enable(i, speed);
} }
@@ -899,7 +899,7 @@ void vlan_dump(void) __banked
/** Set the ingress VLAN filtering */ /** Set the ingress VLAN filtering */
bool port_ingress_vlan_filter_set(uint8_t port, __xdata bool enabled) __banked bool port_ingress_vlan_filter_set(uint8_t port, __xdata bool enabled) __banked
{ {
if (port < machine.min_port || port > machine.max_port && port != CPU_PORT) { if (port < machine.min_port || (port > machine.max_port && port != CPU_PORT)) {
return false; return false;
} }
if (enabled) if (enabled)
@@ -913,7 +913,7 @@ bool port_ingress_vlan_filter_set(uint8_t port, __xdata bool enabled) __banked
/** Get the ingress VLAN filtering status */ /** Get the ingress VLAN filtering status */
bool port_ingress_vlan_filter_get(uint8_t port) __banked bool port_ingress_vlan_filter_get(uint8_t port) __banked
{ {
if (port < machine.min_port || port > machine.max_port && port != CPU_PORT) { if (port < machine.min_port || (port > machine.max_port && port != CPU_PORT)) {
return false; return false;
} }