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Add 10G/5G speed configuration/display

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logicog
2026-04-24 10:53:05 +02:00
parent ec5f74bbed
commit 63ab6500c0
3 changed files with 37 additions and 10 deletions
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rtl837x_init.c
+13 -5
View File
@@ -77,14 +77,17 @@ void static sds_init(void)
pval = SFR_DATA_U16;
sds_write_v(0, 0, 0, pval | 0x200);
}
}
if (machine.n_10g) {
} else if (machine.n_10g == 1) {
reg_read_m(RTL837X_CFG_PHY_MDI_REVERSE);
sfr_mask_data(0, 0x0f,0x0c);
reg_write_m(RTL837X_CFG_PHY_MDI_REVERSE);
REG_SET(RTL837X_CFG_PHY_TX_POLARITY_SWAP, 0x0000596a);
} else if (machine.n_10g == 2) {
REG_SET(RTL837X_CFG_PHY_MDI_REVERSE, 0xc);
REG_SET(RTL837X_CFG_PHY_TX_POLARITY_SWAP, 0x0000596a);
}
}
print_string("\nsds_init done\n");
}
@@ -190,15 +193,20 @@ void rtl8372_init(void)
print_string("\nrtl8372_init called\n");
sds_init();
phy_config(8); // PHY configuration: External 8221B?
if (machine.n_10g != 2)
phy_config(8); // PHY configuration: External 8221B?
if (machine.n_10g)
phy_config_8261(3);
phy_config_8261(3, 0);
if (machine.n_10g == 2)
phy_config_8261(8, 1);
else
phy_config(3); // PHY configuration: all internal PHYs?
// Set the MAC SerDes Modes Bits 0-4: SDS 0 = 0x2 (0x2), Bits 5-9: SDS 1: 1f (off)
// r7b20:00000bff R7b20-00000bff r7b20:00000bff R7b20-00000bff r7b20:00000bff R7b20-000003ff r7b20:000003ff R7b20-000003e2 r7b20:000003e2 R7b20-000003e2
if (machine.n_10g) {
if (machine.n_10g == 1) {
REG_SET(RTL837X_REG_SDS_MODES, 0x3ed); // Disable SFP for now, set RTL8261BE SDS 0 to 0xd
} else if(machine.n_10g == 2) {
REG_SET(RTL837X_REG_SDS_MODES, 0x1ad); // Both 10g ports use SDS_QXGMII
} else {
reg_read_m(RTL837X_REG_SDS_MODES);
sfr_mask_data(1, 0, 0x03);
rtl837x_phy.c
+20 -1
View File
@@ -263,6 +263,10 @@ void phy_set_speed(void) __banked
uint16_t v;
print_string("Setting port "); write_char(machine.log_to_phys_port[phy_settings.port] + '0');
if (machine.n_10g && phy_settings.port == 3)
phy_settings.is10g_port = 1;
if (machine.n_10g == 2 && phy_settings.port == 8)
phy_settings.is10g_port = 1;
if (phy_settings.speed == PHY_OFF) {
print_string(" to disabled");
} else {
@@ -270,6 +274,8 @@ void phy_set_speed(void) __banked
switch(phy_settings.speed) {
case PHY_SPEED_AUTO:
print_string("auto");
if (phy_settings.is10g_port)
print_string (" (10g)");
break;
case PHY_SPEED_10M:
print_string("10M");
@@ -316,7 +322,10 @@ void phy_set_speed(void) __banked
// bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD
phy_write(phy_settings.port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6081);
// GBCR (1000Base-T Control Register, MMD 31.0xA412)
phy_modify(phy_settings.port, PHY_MMD31, PHY_MMD31_GBCR, 0x0000, 0x0200); // Loop timing enabled
if (phy_settings.is10g_port)
phy_modify(phy_settings.port, PHY_MMD31, PHY_MMD31_GBCR, 0x0000, 0x0e00);
else
phy_modify(phy_settings.port, PHY_MMD31, PHY_MMD31_GBCR, 0x0000, 0x0200);
phy_write(phy_settings.port, PHY_MMD_AN, PHY_ANEG_CTRL, 0x3200); // Restart AN
} else {
// AN Control Register (MMD 7.0x0000)
@@ -355,6 +364,12 @@ void phy_set_speed(void) __banked
phy_write(phy_settings.port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6081);
// GBCR (1000Base-T Control Register, MMD 31.0xA412)
phy_modify(phy_settings.port, PHY_MMD31, PHY_MMD31_GBCR, 0x0200, 0x0000);
} else if (phy_settings.speed == PHY_SPEED_5G) {
phy_write(phy_settings.port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6081);
phy_modify(phy_settings.port, PHY_MMD31, PHY_MMD31_GBCR, 0x0400, 0x0000);
} else if (phy_settings.speed == PHY_SPEED_10G) {
phy_write(phy_settings.port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6081);
phy_modify(phy_settings.port, PHY_MMD31, PHY_MMD31_GBCR, 0x0800, 0x0000);
}
}
phy_write(phy_settings.port, PHY_MMD_AN, PHY_ANEG_CTRL, 0x3000); // Enable AN
@@ -512,6 +527,10 @@ void phy_show(uint8_t port) __banked
v = SFR_DATA_U16;
if (v & 0x0080)
print_string(" 2500BaseN-Full");
if (v & 0x0100)
print_string(" 5000BaseN-Full");
if (v & 0x1000)
print_string(" 10GBaseN-Full");
}
phy_read(port, PHY_MMD_AN, PHY_ANEG_LP_ABILITY);
v = SFR_DATA_U16;
rtl837x_port.c
+4 -4
View File
@@ -580,7 +580,7 @@ void port_eee_status(uint8_t port) __banked
if (v & PHY_EEE_BIT_10G)
print_string(" 10G");
else
print_string(" ");
print_string(" ");
}
phy_read(port, PHY_MMD_AN, PHY_EEE_ADV2);
v = SFR_DATA_U16;
@@ -588,7 +588,7 @@ void port_eee_status(uint8_t port) __banked
if (v & PHY_EEE_BIT_5G)
print_string(" 5G");
else
print_string(" ");
print_string(" ");
}
v = SFR_DATA_U16;
if (v & PHY_EEE_BIT_2G5)
@@ -613,7 +613,7 @@ void port_eee_status(uint8_t port) __banked
if (v & PHY_EEE_BIT_10G)
print_string(" 10G");
else
print_string(" ");
print_string(" ");
}
phy_read(port, PHY_MMD_AN, PHY_EEE_LP_ABILITY2);
v = SFR_DATA_U16;
@@ -621,7 +621,7 @@ void port_eee_status(uint8_t port) __banked
if (v & PHY_EEE_BIT_5G)
print_string(" 5G");
else
print_string(" ");
print_string(" ");
}
if (v & PHY_EEE_BIT_2G5)
print_string(" 2.5G");