diff --git a/cmd_parser.c b/cmd_parser.c index 4538c3d..361670a 100644 --- a/cmd_parser.c +++ b/cmd_parser.c @@ -25,6 +25,7 @@ extern __xdata uint8_t nSFPPorts; extern __xdata uint8_t isRTL8373; extern __xdata uint16_t mpos; extern __xdata uint8_t stpEnabled; +extern __code uint8_t log_to_phys_port[9]; extern volatile __xdata uint32_t ticks; extern volatile __xdata uint8_t sfr_data[4]; @@ -632,6 +633,27 @@ void cmd_parser(void) __banked if (cmd_compare(0, "regset")) { parse_regset(); } + if (cmd_compare(0, "eee")) { + int8_t port = -1; + if (cmd_words_b[2] > 0) { + port = cmd_buffer[cmd_words_b[2]] - '1'; + if (!isRTL8373) + port = phys_to_log_port[port]; + } + if (cmd_words_b[1] > 0 && cmd_compare(1, "on")) { + print_string("EEE enabled\n"); + if (port >= 0) + port_eee_enable(port); + else + port_eee_enable_all(); + } else if (cmd_words_b[1] > 0 && cmd_compare(1, "off")) { + print_string("EEE disabled\n"); + if (port >= 0) + port_eee_disable(port); + else + port_eee_disable_all(); + } + } } } diff --git a/html/index.html b/html/index.html index 1dfaaba..765f065 100644 --- a/html/index.html +++ b/html/index.html @@ -1,9 +1,8 @@ - - - - + + + FreeSwitchOS Main Page @@ -21,6 +20,6 @@ + - diff --git a/html/stat.html b/html/stat.html index f91f9b4..467f0bf 100644 --- a/html/stat.html +++ b/html/stat.html @@ -2,9 +2,8 @@ - - - FreeSwitchOS Port Statistics + + FreeSwitchOS Port Statistics diff --git a/html/update.html b/html/update.html index b68b70f..de94719 100644 --- a/html/update.html +++ b/html/update.html @@ -14,6 +14,6 @@ Choose a firmware update file to upload:
+ - diff --git a/html/vlan.html b/html/vlan.html index 5a5265c..27a40d1 100644 --- a/html/vlan.html +++ b/html/vlan.html @@ -2,9 +2,8 @@ - - - FreeSwitchOS VLAN Configuration + + FreeSwitchOS VLAN Configuration @@ -30,6 +29,6 @@ + - diff --git a/httpd/httpd.c b/httpd/httpd.c index b376399..98f0d24 100644 --- a/httpd/httpd.c +++ b/httpd/httpd.c @@ -419,7 +419,7 @@ void httpd_appcall(void) } else if (!strcmp(q, "/vlan.json")) { parse_short(q + 15); send_vlan(short_parsed); - } else if (!strcmp(q, "/counters.json")) { + } else if (is_word(q, "/counters.json")) { send_counters(q[19]-'0'); } else { send_not_found(); diff --git a/phy.h b/phy.h new file mode 100644 index 0000000..3918415 --- /dev/null +++ b/phy.h @@ -0,0 +1,26 @@ +#ifndef _PHY_H_ +#define _PHY_H_ + +/* + * The RTL8272/RTL8273 appear to comprise an RTL8224 PHY + * which in turn is a 4x RTL8221B PHY + * These phys are all Clause 45 + * The defines below are taken from the RTL8221B datasheet + */ + +/* + * Define PHY pages + */ +#define PHY_MMD_AN 7 +#define PHY_MMD_CTRL 31 + + +/* + * Define registers in Auto-Negotiation page + */ +#define PHY_ANEG_CTRL 0x00 +#define PHY_EEE_ADV 0x3c +#define PHY_EEE_ABILITY 0x3d +#define PHY_EEE_ADV2 0x3e + +#endif diff --git a/rtl837x_phy.c b/rtl837x_phy.c index 7cf76e2..420976e 100644 --- a/rtl837x_phy.c +++ b/rtl837x_phy.c @@ -14,6 +14,7 @@ #include "rtl837x_sfr.h" #include "rtl837x_regs.h" #include "rtl837x_phy.h" +#include "phy.h" #pragma codeseg BANK1 @@ -92,7 +93,6 @@ void rtl8224_phy_enable(void) __banked void phy_config(uint8_t phy) __banked { - uint16_t pval; print_string("\r\nphy_config: "); write_char('0' + phy); @@ -199,26 +199,43 @@ void phy_set_mode(uint8_t port, uint8_t speed, uint8_t flow_control, uint8_t dup if (speed == PHY_SPEED_AUTO) { // AN Advertisement Register (MMD 7.0x0010) - phy_write(port, 0x07, 0x10, 0x1001); // bits 0-4: 0x1 (802.3 supported), Extended Next Page format used + phy_write(port, PHY_MMD_AN, 0x10, 0x1001); // bits 0-4: 0x1 (802.3 supported), Extended Next Page format used // Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020) - phy_write(port, 0x07, 0x20, 0x6081); // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD Loop timin enableed - phy_write(port, 0x07, 0x00, 0x3200); // Restart AN + phy_write(port, PHY_MMD_AN, 0x20, 0x6081); // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD Loop timin enableed + phy_write(port, PHY_MMD_AN, 0x00, 0x3200); // Restart AN } else { // AN Control Register (MMD 7.0x0000) - phy_write(port, 0x07, 0x00, 0x2000); // Clear bit 12: No Autoneg, Set Extended Pages (bit 13) + phy_write(port, PHY_MMD_AN, 0x00, 0x2000); // Clear bit 12: No Autoneg, Set Extended Pages (bit 13) // AN Advertisement Register (MMD 7.0x0010) - phy_write(port, 0x07, 0x10, 0x1001); // bits 0-4: 0x1 (802.3 supported), Extended Next Page format used + phy_write(port, PHY_MMD_AN, 0x10, 0x1001); // bits 0-4: 0x1 (802.3 supported), Extended Next Page format used if (speed == PHY_SPEED_1G) { // Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020) - phy_write(port, 0x07, 0x20, 0x6001); // bit 14: SLAVE, bit 13: Multi-Port device, 1: LD Loop timin enableed + phy_write(port, PHY_MMD_AN, 0x20, 0x6001); // bit 14: SLAVE, bit 13: Multi-Port device, 1: LD Loop timin enableed // GBCR (1000Base-T Control Register, MMD 31.0xA412) phy_modify(port, 0x1f, 0xa412, 0x0000, 0x02000); } else if (speed == PHY_SPEED_2G5) { // Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020) - phy_write(port, 0x07, 0x20, 0x6081); // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD Loop timin enableed + phy_write(port, PHY_MMD_AN, 0x20, 0x6081); // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD Loop timin enableed // GBCR (1000Base-T Control Register, MMD 31.0xA412) phy_modify(port, 0x1f, 0xa412, 0x02000, 0x0000); } - phy_write(port, 0x07, 0x00, 0x3200); // Enable AN + phy_write(port, PHY_MMD_AN, 0x00, 0x3200); // Enable AN } } + + +void phy_reset(uint8_t port) __banked +{ + uint16_t v; + phy_read(port, PHY_MMD_CTRL, 0xa610); + v = SFR_DATA_U16; + // If PHY off, do nothing + if (v & 0x0800) + return; + + // Disable PHY + phy_write(port, PHY_MMD_CTRL, 0xa610, v | 0x0800); + delay(5); + // Re-enable PHY + phy_write(port, PHY_MMD_CTRL, 0xa610, v & 0xf7ff); +} diff --git a/rtl837x_phy.h b/rtl837x_phy.h index 9a471c2..fac191c 100644 --- a/rtl837x_phy.h +++ b/rtl837x_phy.h @@ -10,5 +10,6 @@ void rtl8224_phy_enable(void) __banked; void phy_config(uint8_t phy) __banked; void phy_config_8224(void) __banked; void phy_set_mode(uint8_t port, uint8_t speed, uint8_t flow_control, uint8_t duplex) __banked; +void phy_reset(uint8_t port) __banked; #endif diff --git a/rtl837x_port.c b/rtl837x_port.c index 4383bf0..c603c75 100644 --- a/rtl837x_port.c +++ b/rtl837x_port.c @@ -11,6 +11,8 @@ #include "rtl837x_sfr.h" #include "rtl837x_regs.h" #include "rtl837x_port.h" +#include "rtl837x_phy.h" +#include "phy.h" #pragma codeseg BANK1 @@ -477,6 +479,52 @@ uint16_t port_isolation_get(register uint8_t port) } +void port_eee_enable(uint8_t port) __banked +{ + if (is_sfp[port]) + return; + + print_string("EEE on for "); print_byte(port); write_char('\n'); + REG_SET(RTL8373_EEE_CTRL_BASE + (port << 2), EEE_100 | EEE_1000 | EEE_2G5); + // Enable EEE advertisement for 100/1000BASE-T via EEE Advertisement Reg + phy_write(port, PHY_MMD_AN, PHY_EEE_ADV, 6); // Bit 1: 100BASE-T, Bit 2: 1000BASE-T + // Enable EEE advertisement for 2.5GBASE-T via EEE Advertisement Reg 2 + phy_write(port, PHY_MMD_AN, PHY_EEE_ADV2, 1); + phy_reset(port); +} + + +void port_eee_disable(uint8_t port) __banked +{ + if (is_sfp[port]) + return; + + print_string("EEE off for "); print_byte(port); write_char('\n'); + REG_SET(RTL8373_EEE_CTRL_BASE + (port << 2), 0); + // Enable EEE advertisement for 100/1000BASE-T via EEE Advertisement Reg + phy_write(port, PHY_MMD_AN, PHY_EEE_ADV, 0); + // Enable EEE advertisement for 2.5GBASE-T via EEE Advertisement Reg 2 + phy_write(port, PHY_MMD_AN, PHY_EEE_ADV2, 0); + phy_reset(port); +} + + +void port_eee_enable_all(void) __banked +{ + for (uint8_t i = minPort; i <= maxPort; i++) { + port_eee_enable(i); + } +} + + +void port_eee_disable_all(void) __banked +{ + for (uint8_t i = minPort; i <= maxPort; i++) { + port_eee_disable(i); + } +} + + /* * Enable RLDP, Realtek's version of LLDP */ diff --git a/rtl837x_port.h b/rtl837x_port.h index 22bcf61..81eec4c 100644 --- a/rtl837x_port.h +++ b/rtl837x_port.h @@ -27,4 +27,8 @@ void port_mirror_del(void) __banked; void port_ingress_filter(register uint8_t port, uint8_t type) __banked; void port_l2_setup(void) __banked; void trunk_set(uint8_t group, uint16_t mask) __banked; +void port_eee_enable_all(void) __banked; +void port_eee_disable_all(void) __banked; +void port_eee_enable(uint8_t port) __banked; +void port_eee_disable(uint8_t port) __banked; #endif diff --git a/rtl837x_regs.h b/rtl837x_regs.h index 2ab37db..b0e82bb 100644 --- a/rtl837x_regs.h +++ b/rtl837x_regs.h @@ -150,12 +150,20 @@ /* * Loop detection / STP */ - #define RTL8373_RLDP_TIMER 0x1074 #define RTL837X_RMA0_CONF 0x4ecc #define RTL837X_RMA_CONF 0x4f1c #define RTL837X_MSTP_STATES 0x5310 +/* + * EEE + */ +#define RTL8373_EEE_CTRL_BASE 0x606c +#define EEE_100 0x01 +#define EEE_1000 0x04 +#define EEE_2G5 0x10 + + #ifdef REGDBG #define REG_SET(r, v) SFR_DATA_24 = (((uint32_t)v) >> 24) & 0xff; \