From 51ed063dcb6da15d2a7bdc08a0160b5795a415f3 Mon Sep 17 00:00:00 2001 From: robs Date: Sat, 24 Oct 2026 08:30:27 +0200 Subject: [PATCH] rtl8372_init: set SDS 0 to SGMII as the stock firmware does The masks were 0, so 0x3e2 was ORed into the reset value 0xbff and both SerDes stayed off on boards without 10G ports (n_10g == 0), e.g. the HC-SWTG124AS. With SDS 0 off RTL837X_REG_SEC_COUNTER does not hold a written value: it reads 0, so NTP never retried after a failed first attempt at boot and froze the clock after a sync. Tested with regset on an HC-SWTG124AS: the register keeps a write with SDS 0 in SGMII or 10GR, not with SDS 0 off (also not with only SDS 1 on). --- rtl837x_init.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/rtl837x_init.c b/rtl837x_init.c index 73498642..cc2adfcd 100644 --- a/rtl837x_init.c +++ b/rtl837x_init.c @@ -221,9 +221,11 @@ void rtl8372_init(void) __banked } else if(machine.n_10g == 2) { REG_SET(RTL837X_REG_SDS_MODES, 0x1ad); // Both 10g ports use SDS_QXGMII } else { + // Replace the reset value 0xbff (both SDS off) instead of ORing into it: + // RTL837X_REG_SEC_COUNTER only holds a written value while SDS 0 is on reg_read_m(RTL837X_REG_SDS_MODES); - sfr_mask_data(1, 0, 0x03); - sfr_mask_data(0, 0, 0xe2); + sfr_mask_data(1, 0xff, 0x03); + sfr_mask_data(0, 0xff, 0xe2); reg_write_m(RTL837X_REG_SDS_MODES); }