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Handle RTL8261BE SerDes configuration

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The RTL8261BE uses a 10GBit QSGMII connection. Add handler for initial
configuration of the SerDes speed and upon link changes.
This commit is contained in:
logicog
2026-04-24 10:52:24 +02:00
parent c8e21b394b
commit 4f4f69ecc1
2 changed files with 64 additions and 31 deletions
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rtl837x_init.c
+31 -26
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@@ -19,14 +19,6 @@ extern __xdata struct machine_runtime machine_detected;
*/
void static sds_init(void)
{
/*
p001e.000d:9535 R02f8-00009535 R02f4-0000953a P000001.1e00000d:953a
p001e.000d:953a p001e.000d:953a R02f8-0000953a R02f4-00009530 P000001.1e00000d:9530
RTL8373:
p001e.000d:0010 R02f8-00000010 R02f4-0000001a P000001.1e00000d:b7fe
p001e.000d:0010 p001e.000d:0010 R02f8-00000010 R02f4-00000010 P000001.1e00000d:b7fe
*/
phy_read(0, PHY_MMD30, 0xd);
uint16_t pval = SFR_DATA_U16;
@@ -55,6 +47,8 @@ void static sds_init(void)
uint16_t pval;
print_string(" N-settings");
if (machine.n_10g)
print_string(" - 10g");
// Serdes 0 RX PN swap for 64B/66B
sds_read(1, 6, 2);
pval = SFR_DATA_U16;
@@ -70,23 +64,31 @@ void static sds_init(void)
pval = SFR_DATA_U16;
sds_write_v(0, 6, 2, pval | 0x2000);
if (machine_detected.isRTL8373) {
// RTL8224: Serdes 0 RX PN swap for 64B/66B
// We assume that RTL8373N always paired with RTL8224N.
// This sds register value is 0x0000 at reset.
// So only write to it.
RTL8224_SDS_WRITE(0, 6, 2, 0x2000);
} else {
// Serdes 0 RX PN swap for 8B/10B
sds_read(0, 0, 0);
pval = SFR_DATA_U16;
sds_write_v(0, 0, 0, pval | 0x200);
if (!machine.n_10g) {
if (machine_detected.isRTL8373) {
// RTL8224: Serdes 0 RX PN swap for 64B/66B
// We assume that RTL8373N always paired with RTL8224N.
// This sds register value is 0x0000 at reset.
// So only write to it.
RTL8224_SDS_WRITE(0, 6, 2, 0x2000);
} else {
// Serdes 0 RX PN swap for 8B/10B
sds_read(0, 0, 0);
pval = SFR_DATA_U16;
sds_write_v(0, 0, 0, pval | 0x200);
}
}
if (machine.n_10g) {
reg_read_m(RTL837X_CFG_PHY_MDI_REVERSE);
sfr_mask_data(0, 0x0f,0x0c);
reg_write_m(RTL837X_CFG_PHY_MDI_REVERSE);
REG_SET(RTL837X_CFG_PHY_TX_POLARITY_SWAP, 0x0000596a);
}
}
}
void rtl8373_init(void) __banked
void rtl8373_init(void)
{
print_string("\nrtl8373_init called\n");
@@ -183,7 +185,7 @@ void rtl8373_init(void) __banked
}
void rtl8372_init(void) __banked
void rtl8372_init(void)
{
print_string("\nrtl8372_init called\n");
@@ -192,11 +194,14 @@ void rtl8372_init(void) __banked
phy_config(3); // PHY configuration: all internal PHYs?
// Set the MAC SerDes Modes Bits 0-4: SDS 0 = 0x2 (0x2), Bits 5-9: SDS 1: 1f (off)
// r7b20:00000bff R7b20-00000bff r7b20:00000bff R7b20-00000bff r7b20:00000bff R7b20-000003ff r7b20:000003ff R7b20-000003e2 r7b20:000003e2 R7b20-000003e2
reg_read_m(RTL837X_REG_SDS_MODES);
sfr_mask_data(1, 0, 0x03);
sfr_mask_data(0, 0, 0xe2);
reg_write_m(RTL837X_REG_SDS_MODES);
if (machine.n_10g) {
REG_SET(RTL837X_REG_SDS_MODES, 0x3ed); // Disable SFP for now, set RTL8261BE SDS 0 to 0xd
} else {
reg_read_m(RTL837X_REG_SDS_MODES);
sfr_mask_data(1, 0, 0x03);
sfr_mask_data(0, 0, 0xe2);
reg_write_m(RTL837X_REG_SDS_MODES);
}
// r0a90:000000f3 R0a90-000000fc
reg_read_m(RTL837X_CFG_PHY_MDI_REVERSE);
sfr_mask_data(0, 0x0f, 0x0c);