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https://github.com/logicog/RTLPlayground.git
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Merge pull request #66 from vDorst/fix_systick_asm
Move SYS_TICK to Timer2 and SERIAL baudrate gen to Timer1.
This commit is contained in:
logicog
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+92
-45
@@ -28,7 +28,7 @@ void crc16(__xdata uint8_t *v) __naked;
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// Upload Firmware to 1M
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#define FIRMWARE_UPLOAD_START 0x100000
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#define SYS_TICK_HZ 200
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// See setup_serial_timer1() for valid baudrate settings!
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#define SERIAL_BAUD_RATE 115200
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/* All RTL839x switches have an external 25MHz Oscillator,
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@@ -54,12 +54,20 @@ void crc16(__xdata uint8_t *v) __naked;
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#define CLOCK_DIV 0
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#endif
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// Derive divider for the system ticks
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#define TIMER0_DIV (CLOCK_HZ / 12 / SYS_TICK_HZ)
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#if TIMER0_DIV > 0xFFFF
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#error "SYS_TICH_HZ to low, must be >= 158"
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/* Derive divider for the system ticks
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TIMER2 can divide the F_CPU by 4 or 12.
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So the F_TICKS are in the range of:
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- F_TIMER_DIV4_OVERFLOW = F_SYS / DIV4 / 1..65536 = 125MHz / 4 / 1..65536 = 31.25 MHz .. 476.8 Hz
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- T_TIMER_DIV12_OVERFLOW = F_SYS / DIV12 / 1..65536 = 125MHz / 12 / 1..65536 = 10.42 MHz .. 158.9 Hz
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Selecting dividor 12 settings to get lowest timer tick posiable which is already high.
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*/
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#define SYS_TICK_HZ 200
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#define TIMER2_DIV (CLOCK_HZ / 12 / SYS_TICK_HZ)
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#if TIMER2_DIV > 0xFFFF
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#error "SYS_TICK_HZ to low, must be >= 159"
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#endif
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#define SYSTICK_TIMER0_VALUE (0x10000 - TIMER0_DIV)
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#define SYSTICK_TIMER2_VALUE (0x10000 - TIMER2_DIV)
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__xdata uint8_t idle_ready;
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@@ -113,29 +121,38 @@ __xdata char sfp_module_vendor[2][17];
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__xdata char sfp_module_model[2][17];
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__xdata char sfp_module_serial[2][17];
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__xdata uint8_t sfp_options[2];
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__sbit tx_buf_empty;
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#define ETHERTYPE_OFFSET (12 + VLAN_TAG_SIZE + RTL_TAG_SIZE)
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void isr_timer0(void) __interrupt(1)
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{
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TR0 = 0; // Stop timer 0
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T0_U16 = SYSTICK_TIMER0_VALUE;
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TR0 = 1; // Re-start timer 0
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}
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// Timer2: Handle SYS_TICK
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void isr_timer2(void) __interrupt(5)
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{
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ticks++;
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if (sleep_ticks > 0)
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sleep_ticks--;
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sec_counter++;
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// Clear TF2 & EXF2 by software
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T2CON &= ~0xC0;
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}
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void isr_serial(void) __interrupt(4)
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{
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if (RI == 1) {
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RI = 0;
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sbuf[sbuf_ptr] = SBUF;
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sbuf_ptr = (sbuf_ptr + 1) & (SBUF_SIZE - 1);
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RI = 0;
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}
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if (TI == 1) {
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TI = 0;
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tx_buf_empty = 1;
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}
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}
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@@ -143,14 +160,14 @@ void isr_serial(void) __interrupt(4)
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void write_char(char c)
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{
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do {
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} while (TI == 0);
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TI = 0;
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} while (tx_buf_empty == 0);
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if (c =='\n') {
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tx_buf_empty = 0;
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SBUF = '\r';
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do {
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} while (TI == 0);
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TI = 0;
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} while (tx_buf_empty == 0);
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}
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tx_buf_empty = 0;
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SBUF = c;
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}
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@@ -287,18 +304,25 @@ void isr_ext3(void) __interrupt(9)
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write_char('W');
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}
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void setup_timer0(void)
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// Timer2: handles system tick.
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void setup_timer2(void)
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{
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TMOD = 0x11; // Timer 1: Mode 1, Timer 0: Mode 1, i.e. 16 bit counters, no auto-reload
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/* The TH0 registers contain the high/low byte that we load into Timer0 when T0
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* overflows to 0x10000
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*/
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T0_U16 = SYSTICK_TIMER0_VALUE;
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T2CON = 0x00; // Timer2: Mode 16-bit timer with auto-reload, disable the timer.
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// Timer 2 clock select F_SYS / 12;
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// T2M = 0 uses clk/12;
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CKCON &= ~0x20;
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// The RCAP2 registers contain the high/low byte that is loaded into
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// timer2 when T2 overflows to 0x10000
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RCAP2_U16 = SYSTICK_TIMER2_VALUE;
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T2CON |= 0x04; // Timer2: Enable
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// IP |= 0x20; // TEST: Make Timer 2 interrupt as high priority.
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ET2 = 1; // Enable Timer2 interrupt.
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CKCON &= 0xc7;
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TCON = 0x10; // Start timer 0
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ET0 = 1; // Enable timer interrupts
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}
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@@ -1646,27 +1670,52 @@ void init_smi(void)
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}
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/* Set up serial port 0 using Timer 2 with an external trigger
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* as baud generator.
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* The external clock generator uses a crystal at 25MHz.
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/* Set up serial port 0 using Timer 1 as baudrate generator.
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* For x Bd these settings are needed, see table below.
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* NOTE: Settings only valid for F_SYS = 125 MHz!
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* | Wanted | | TMR | F_SYS | | Actual | |
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* | baudrate | SMOD0 | DIV | DIV | TH1 | baudrate | Error |
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* | -------- | ----- | --- | ----- | ---- | -------- | ------ |
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* | 1200 | 0 | 12 | 255 | 0x01 | 1276.6 | 6.00% |
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* | 2400 | 0 | 12 | 136 | 0x78 | 2393.5 | −0.27% |
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* | 4800 | 0 | 4 | 203 | 0x35 | 4810.7 | 0.22% |
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* | 9600 | 1 | 4 | 203 | 0x35 | 9621.3 | 0.22% |
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* | 14400 | 1 | 4 | 136 | 0x78 | 14361.2 | −0.27% |
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* | 19200 | 1 | 4 | 102 | 0x9a | 19148.3 | −0.27% |
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* | 38400 | 1 | 4 | 51 | 0xcd | 38296.6 | −0.27% |
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* | 57600 | 1 | 4 | 34 | 0xde | 57444.9 | −0.27% |
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* | 115200 | 1 | 4 | 17 | 0xef | 114889.7 | −0.27% |
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*/
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void setup_serial(void)
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#if CLOCK_HZ != 125000000
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#warning "SERIAL 0 baudrate setting may only valid for F_CPU = 125 MHz!"
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#endif
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void setup_serial_timer1(void)
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{
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IE = 0;
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// Timer 1: Mode 2: automatic reload
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TMOD &= 0x0F;
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TMOD |= 0xA0; // Timer1: GATE, Mode2: Timer, 8-bit with auto-reload
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CKCON |= 0x10; // Timer1 clock divider: F_SYS / 4: T2M = 1, Timer 1 uses clk/4
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T2CON = 0x34; // Enable RCLK/TCLK (serial transmit/receive clock for T2), TR2 (Timer 2 RUN), disable CP/RL2 (bit 0)
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SCON = 0x50; // Mode = 1: ASYNC 8N1 with T2 as baud-rate generator, REN_0 Receive enable
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PCON |= 0x80; // SMOD0 = 1; Double the Baud Rate, don't divide Timer 1 Overflag signal.
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// The RCAP2 registers contain the high/low byte that is loaded into
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// timer2 when T2 overflows to 0x10000
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RCAP2H = (0x10000 - ((CLOCK_HZ / SERIAL_BAUD_RATE + 16) / 32)) >> 8;
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RCAP2L = (0x10000 - ((CLOCK_HZ / SERIAL_BAUD_RATE + 16) / 32)) % 0xff;
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SCON = 0x50; // Mode = 1: ASYNC 8N1 with Timer 2 as baud-rate generator, REN_0 Receive enable
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PCON |= 0x80; // Double the Baud Rate
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/* The TH1 register contain the reload value, timer1 when T1 overflows to 0x100.
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* NOTE: compiler computs the wrong value. 0xF0 is calculated but 0xEF is the right value for 115200.
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* Also https://www.keil.com/products/c51/baudrate.asp confirms this.
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* Added 32 before div by 64 to make sure rounding is correct so that the results are right.
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*
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* TH1 = 0x100 - (2^SMOD0 * F_SYS) / ( TMR1_DIV / BAUDRATE * 32)
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*/
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TH1 = (0x100 - (((CLOCK_HZ / SERIAL_BAUD_RATE) + 32) / (4 * 16))) & 0xff;
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SCON = 0x50;
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TI = 1;
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RI = 0;
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TCON |= 0x40; // Start timer 1
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ET1 = 0; // Timer1 Interrupt is NOT wanted!
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TI = 0; // Clear TI-interrupt flag
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RI = 0; // Clear RI-interrupt flag
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tx_buf_empty = 1; // Set tx `serial buffer is empty`-software flag.
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ES = 1; // Enable serial IRQ
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}
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@@ -1706,16 +1755,14 @@ void bootloader(void)
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IE = 0;
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EIE = 0; // SFR e8: EIE. Disable all external IRQs
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// Disable all interrupts (global interrupt enable bit)
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EA = 0; // SFR A8.7 / IE.7
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idle_ready = 0;
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// HW setup, serial, timer, external IRQs
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setup_clock();
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setup_serial();
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setup_timer0();
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setup_timer2();
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setup_serial_timer1();
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setup_external_irqs();
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EA = 1; // Enable all IRQs
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EA = 1; // Enable global interrupt
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// Set default for SFP pins so we can start up a module already inserted
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sfp_pins_last = 0x33; // signal LOS and no module inserted (for both slots, even if only 1 present)
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