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Merge pull request #673 from andrebrait/fix/xdata-startup
startup: clear SFR 0x97 before the C runtime initialises xdata
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+17
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@@ -47,6 +47,12 @@
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- The web UI and the configuration upload now refuse a line the replay cannot take,
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- The web UI and the configuration upload now refuse a line the replay cannot take,
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instead of writing it to flash.
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instead of writing it to flash.
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- Startup
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- Initialised and zero-initialised globals above xdata 0x4000 now get their values at boot.
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Hardware reset leaves SFR 0x97 at 1, which maps xdata 0x4000-0xbfff to the flash image,
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and it was cleared only in `main()`, after the C startup code had copied and cleared them.
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This showed as a random web session timeout and LLDP blocked on some ports without config.
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## Breaking changes
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## Breaking changes
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- Config
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- Config
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@@ -348,7 +348,7 @@ void installer(void)
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{
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{
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CKCON = 0; // Initial Clock configuration
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CKCON = 0; // Initial Clock configuration
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SFR_97 = 0; // HADDR?
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MAP_FLASH_PAGE_TO_XDATA = 0; // HADDR?
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// Set in managed mode:
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// Set in managed mode:
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SFR_b9 = 0x00;
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SFR_b9 = 0x00;
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+1
-1
@@ -55,7 +55,7 @@ __sfr __at(0xbb) SFR_BANK_RET;
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__sfr __at(0x8e) CKCON;
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__sfr __at(0x8e) CKCON;
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__sfr __at(0x97) SFR_97; // HADDR?
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__sfr __at(0x97) MAP_FLASH_PAGE_TO_XDATA; // 1 (hardware reset default): xdata 0x4000-0xbfff reads the flash image; 0: RAM
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__sfr __at(0xb9) SFR_b9;
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__sfr __at(0xb9) SFR_b9;
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__sfr __at(0xba) SFR_ba;
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__sfr __at(0xba) SFR_ba;
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+9
-1
@@ -1567,6 +1567,15 @@ void check_and_flash_update_image(void)
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}
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}
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/* Called by the SDCC startup code before it copies XINIT to XISEG and clears XSEG.
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* Hardware reset starts us with MAP_FLASH_PAGE_TO_XDATA = 1, which maps xdata
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* 0x4000-0xbfff to the flash image (reads return flash, writes are lost), so it
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* must be 0 by then. */
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unsigned char __sdcc_external_startup(void)
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{
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MAP_FLASH_PAGE_TO_XDATA = 0;
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return 0;
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}
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void main(void)
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void main(void)
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{
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{
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@@ -1577,7 +1586,6 @@ void main(void)
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sbuf_ptr = 0;
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sbuf_ptr = 0;
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CKCON = 0; // Initial Clock configuration
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CKCON = 0; // Initial Clock configuration
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SFR_97 = 0; // HADDR?
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// Set in managed mode:
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// Set in managed mode:
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SFR_b9 = 0x00;
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SFR_b9 = 0x00;
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