From 3d7ef55cedf9d03db9075ef48ba03dd925fdf43b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= Date: Mon, 26 Jan 2026 22:35:03 +0100 Subject: [PATCH] Demagic PHY_MMD31, 0xa412 to PHY_MMD31, PHY_MMD31_GBCR --- httpd/page_impl.c | 2 +- phy.h | 7 +++++++ rtl837x_phy.c | 12 ++++++------ 3 files changed, 14 insertions(+), 7 deletions(-) diff --git a/httpd/page_impl.c b/httpd/page_impl.c index 2a15e75..288e4f4 100644 --- a/httpd/page_impl.c +++ b/httpd/page_impl.c @@ -613,7 +613,7 @@ void send_status(void) phy_read(i, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL); uint16_t w = SFR_DATA_U16; bool_to_html(!!(w & 0x80)); // 2500BaseN-Full - phy_read(i, PHY_MMD31, 0xa412); + phy_read(i, PHY_MMD31, PHY_MMD31_GBCR); w = SFR_DATA_U16; bool_to_html(!!(w & 0x0200)); // 1000Base-Full phy_read(i, PHY_MMD_AN, PHY_ANEG_ADV); diff --git a/phy.h b/phy.h index c92369a..d9f3216 100644 --- a/phy.h +++ b/phy.h @@ -31,6 +31,13 @@ #define PHY_EEE_BIT_1G 0x04 #define PHY_EEE_BIT_100M 0x02 +/* + * MMD 31 Registers + */ +#define PHY_MMD31_GBCR 0xa412 + + + /* * Define registers in Control page */ diff --git a/rtl837x_phy.c b/rtl837x_phy.c index e9ffdbc..dd7bf84 100644 --- a/rtl837x_phy.c +++ b/rtl837x_phy.c @@ -207,7 +207,7 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD phy_write(port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6081); // GBCR (1000Base-T Control Register, MMD 31.0xA412) - phy_modify(port, PHY_MMD31, 0xa412, 0x0000, 0x0200); // Loop timing enabled + phy_modify(port, PHY_MMD31, PHY_MMD31_GBCR, 0x0000, 0x0200); // Loop timing enabled phy_write(port, PHY_MMD_AN, 0x00, 0x3200); // Restart AN } else { // AN Control Register (MMD 7.0x0000) @@ -220,7 +220,7 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked phy_write(port, PHY_MMD_AN, PHY_ANEG_ADV, 0x1441); else phy_write(port, PHY_MMD_AN, PHY_ANEG_ADV, 0x1461); - phy_modify(port, PHY_MMD31, 0xa412, 0x0200, 0x0000); + phy_modify(port, PHY_MMD31, PHY_MMD31_GBCR, 0x0200, 0x0000); } else if (speed == PHY_SPEED_100M) { phy_write(port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6001); if (!duplex) @@ -229,7 +229,7 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked phy_write(port, PHY_MMD_AN, PHY_ANEG_ADV, 0x1501); else phy_write(port, PHY_MMD_AN, PHY_ANEG_ADV, 0x1581); - phy_modify(port, PHY_MMD31, 0xa412, 0x0200, 0x0000); + phy_modify(port, PHY_MMD31, PHY_MMD31_GBCR, 0x0200, 0x0000); } else { // AN Advertisement Register (MMD 7.0x0010) // bits 0-4: 0x1 (802.3 supported), Extended Next Page format used @@ -239,13 +239,13 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked // bit 14: SLAVE, bit 13: Multi-Port device, 1: LD Loop timin enableed phy_write(port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6001); // GBCR (1000Base-T Control Register, MMD 31.0xA412) - phy_modify(port, PHY_MMD31, 0xa412, 0x0000, 0x0200); + phy_modify(port, PHY_MMD31, PHY_MMD31_GBCR, 0x0000, 0x0200); } else if (speed == PHY_SPEED_2G5) { // Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020) // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD Loop timin enableed phy_write(port, PHY_MMD_AN, PHY_ANEG_MGBASE_CTRL, 0x6081); // GBCR (1000Base-T Control Register, MMD 31.0xA412) - phy_modify(port, PHY_MMD31, 0xa412, 0x0200, 0x0000); + phy_modify(port, PHY_MMD31, PHY_MMD31_GBCR, 0x0200, 0x0000); } } phy_write(port, PHY_MMD_AN, 0x00, 0x3000); // Enable AN @@ -384,7 +384,7 @@ void phy_show(uint8_t port) __banked print_string(" 100Base-Half"); if (v & 0x0100) print_string(" 100Base-Full"); - phy_read(port, PHY_MMD31, 0xa412); + phy_read(port, PHY_MMD31, PHY_MMD31_GBCR); v = SFR_DATA_U16; if (v & 0x0200) print_string(" 1000Base-Full");