Do not enter Idle mode from the external interrupt 2 handler

isr_ext2() ends with PCON |= 1, putting the core to sleep from inside an
interrupt handler.

The DW8051 leaves idle when any enabled interrupt is activated, so the core
does not stay down for long. It naps until the next enabled interrupt request
turns up, with the 200 Hz system tick putting a ceiling of 5 ms on that, and
then carries on.

The sleep buys nothing either way, because the instruction after it is the
return. While it lasts the handler holds the priority latch, so everything at
its level or below waits, and that includes the tick, the console and the NIC
receive interrupt.

The handler still clears its flag, which is what it has to do. The bit numbers
beside the two masks were wrong: 0xef clears bit 4 and 0xdf clears bit 5,
not 7 and 6.
This commit is contained in:
d00f committed 2026-09-08 23:35:27 +02:00
1 parent c012dda029
commit 247b230212
1 file changed
+2 -2
+2 -2
View File
@@ -515,7 +515,7 @@ void isr_ext1(void) __interrupt(2)
*/ */
void isr_ext2(void) __interrupt(8) void isr_ext2(void) __interrupt(8)
{ {
EXIF &= 0xef; EXIF &= 0xef; // Clear IRQ flag (bit 4) in EXIF
} }
/* /*
@@ -524,7 +524,7 @@ void isr_ext2(void) __interrupt(8)
*/ */
void isr_ext3(void) __interrupt(9) void isr_ext3(void) __interrupt(9)
{ {
EXIF &= 0xdf; EXIF &= 0xdf; // Clear IRQ flag (bit 5) in EXIF
} }
// Timer2: handles system tick. // Timer2: handles system tick.