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Rename PHY_MMD_CTRL to PHY_MMD31.

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So demagic the `phy_(, 0x1f, )` to `phy_(, PHY_MMD31, )`.
This commit is contained in:
René van Dorst
2026-01-25 23:38:04 +01:00
parent fc327810ed
commit 13d0781455
5 changed files with 30 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files
httpd/page_impl.c
+2 -2
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@@ -607,13 +607,13 @@ void send_status(void)
} }
} else { } else {
slen += strtox(outbuf + slen, ",\"isSFP\":0,\"enabled\":"); slen += strtox(outbuf + slen, ",\"isSFP\":0,\"enabled\":");
phy_read(i, 0x1f, 0xa610); phy_read(i, PHY_MMD31, 0xa610);
bool_to_html(SFR_DATA_8 == 0x20); bool_to_html(SFR_DATA_8 == 0x20);
slen += strtox(outbuf + slen, ",\"adv\":\""); slen += strtox(outbuf + slen, ",\"adv\":\"");
phy_read(i, PHY_MMD_AN, 0x20); phy_read(i, PHY_MMD_AN, 0x20);
uint16_t w = SFR_DATA_U16; uint16_t w = SFR_DATA_U16;
bool_to_html(!!(w & 0x80)); // 2500BaseN-Full bool_to_html(!!(w & 0x80)); // 2500BaseN-Full
phy_read(i, PHY_MMD_CTRL, 0xa412); phy_read(i, PHY_MMD31, 0xa412);
w = SFR_DATA_U16; w = SFR_DATA_U16;
bool_to_html(!!(w & 0x0200)); // 1000Base-Full bool_to_html(!!(w & 0x0200)); // 1000Base-Full
phy_read(i, PHY_MMD_AN, 0x10); phy_read(i, PHY_MMD_AN, 0x10);
phy.h
+1 -1
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@@ -14,7 +14,7 @@
#define PHY_MMD_PMAPMD 1 #define PHY_MMD_PMAPMD 1
#define PHY_MMD_AN 7 #define PHY_MMD_AN 7
#define PHY_SDS_CTRL 30 #define PHY_SDS_CTRL 30
#define PHY_MMD_CTRL 31 #define PHY_MMD31 31
/* /*
* Define registers in Auto-Negotiation page * Define registers in Auto-Negotiation page
rtl837x_phy.c
+21 -21
View File
@@ -103,7 +103,7 @@ void phy_config(uint8_t phy) __banked
// p031f.a432:0811 P000008.1f00a432:0831 // p031f.a432:0811 P000008.1f00a432:0831
// PHYCR2 PHY Specific Control Register 2, MMD 31. 0xA432), set bit 5: enable EEE // PHYCR2 PHY Specific Control Register 2, MMD 31. 0xA432), set bit 5: enable EEE
phy_modify(phy, 0x1f, 0xa432, 0x0000, 0x0020); phy_modify(phy, PHY_MMD31, 0xa432, 0x0000, 0x0020);
// p0307.003e:0000 P000008.0700003e:0001 // p0307.003e:0000 P000008.0700003e:0001
// EEE avertisment 2 register MMMD 7.0x003e, set bit 0: 2.5G has EEE capability // EEE avertisment 2 register MMMD 7.0x003e, set bit 0: 2.5G has EEE capability
@@ -112,7 +112,7 @@ void phy_config(uint8_t phy) __banked
// p031f.a442:043c P000008.1f00a442:0430 // p031f.a442:043c P000008.1f00a442:0430
// Unknown, but clear bits 2/3 // Unknown, but clear bits 2/3
phy_modify(phy, 0x1f, 0xa442, 0x000c, 0x0000); phy_modify(phy, PHY_MMD31, 0xa442, 0x000c, 0x0000);
delay(20); delay(20);
// P000100.1e0075b5:e084 // P000100.1e0075b5:e084
@@ -133,10 +133,10 @@ void phy_config(uint8_t phy) __banked
// p031f.a400:1040 P000008.1f00a400:5040, then: p031f.a400:5040 P000008.1f00a400:1040 // p031f.a400:1040 P000008.1f00a400:5040, then: p031f.a400:5040 P000008.1f00a400:1040
// FEDCR (Fast Ethernet Duplex Control Register, MMD 31.0xA400) // FEDCR (Fast Ethernet Duplex Control Register, MMD 31.0xA400)
// Set bit 14, sleep, then clear again, according to the datasheet these bits are reserved // Set bit 14, sleep, then clear again, according to the datasheet these bits are reserved
phy_modify(phy, 0x1f, 0xa400, 0x0000, 0x4000); phy_modify(phy, PHY_MMD31, 0xa400, 0x0000, 0x4000);
delay(20); delay(20);
phy_modify(phy, 0x1f, 0xa400, 0x4000, 0x0000); phy_modify(phy, PHY_MMD31, 0xa400, 0x4000, 0x0000);
delay(20); delay(20);
print_string("\r\n phy config done\r\n"); print_string("\r\n phy config done\r\n");
@@ -190,15 +190,15 @@ void phy_config_8224(void) __banked
void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked
{ {
uint16_t v; uint16_t v;
phy_read(port, PHY_MMD_CTRL, 0xa610); phy_read(port, PHY_MMD31, 0xa610);
v = SFR_DATA_U16; v = SFR_DATA_U16;
if (speed == PHY_OFF) { if (speed == PHY_OFF) {
phy_write(port, PHY_MMD_CTRL, 0xa610, v | 0x0800); phy_write(port, PHY_MMD31, 0xa610, v | 0x0800);
return; return;
} }
// Port is on, make sure of it: // Port is on, make sure of it:
if (v & 0x0800) if (v & 0x0800)
phy_write(port, PHY_MMD_CTRL, 0xa610, v & 0xf7ff); phy_write(port, PHY_MMD31, 0xa610, v & 0xf7ff);
if (speed == PHY_SPEED_AUTO) { if (speed == PHY_SPEED_AUTO) {
// AN Advertisement Register (MMD 7.0x0010) // AN Advertisement Register (MMD 7.0x0010)
@@ -208,7 +208,7 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked
// bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD
phy_write(port, PHY_MMD_AN, 0x20, 0x6081); phy_write(port, PHY_MMD_AN, 0x20, 0x6081);
// GBCR (1000Base-T Control Register, MMD 31.0xA412) // GBCR (1000Base-T Control Register, MMD 31.0xA412)
phy_modify(port, PHY_MMD_CTRL, 0xa412, 0x0000, 0x0200); // Loop timing enabled phy_modify(port, PHY_MMD31, 0xa412, 0x0000, 0x0200); // Loop timing enabled
phy_write(port, PHY_MMD_AN, 0x00, 0x3200); // Restart AN phy_write(port, PHY_MMD_AN, 0x00, 0x3200); // Restart AN
} else { } else {
// AN Control Register (MMD 7.0x0000) // AN Control Register (MMD 7.0x0000)
@@ -221,7 +221,7 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked
phy_write(port, PHY_MMD_AN, 0x10, 0x1441); phy_write(port, PHY_MMD_AN, 0x10, 0x1441);
else else
phy_write(port, PHY_MMD_AN, 0x10, 0x1461); phy_write(port, PHY_MMD_AN, 0x10, 0x1461);
phy_modify(port, PHY_MMD_CTRL, 0xa412, 0x0200, 0x0000); phy_modify(port, PHY_MMD31, 0xa412, 0x0200, 0x0000);
} else if (speed == PHY_SPEED_100M) { } else if (speed == PHY_SPEED_100M) {
phy_write(port, PHY_MMD_AN, 0x20, 0x6001); phy_write(port, PHY_MMD_AN, 0x20, 0x6001);
if (!duplex) if (!duplex)
@@ -230,7 +230,7 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked
phy_write(port, PHY_MMD_AN, 0x10, 0x1501); phy_write(port, PHY_MMD_AN, 0x10, 0x1501);
else else
phy_write(port, PHY_MMD_AN, 0x10, 0x1581); phy_write(port, PHY_MMD_AN, 0x10, 0x1581);
phy_modify(port, PHY_MMD_CTRL, 0xa412, 0x0200, 0x0000); phy_modify(port, PHY_MMD31, 0xa412, 0x0200, 0x0000);
} else { } else {
// AN Advertisement Register (MMD 7.0x0010) // AN Advertisement Register (MMD 7.0x0010)
// bits 0-4: 0x1 (802.3 supported), Extended Next Page format used // bits 0-4: 0x1 (802.3 supported), Extended Next Page format used
@@ -240,13 +240,13 @@ void phy_set_speed(uint8_t port, uint8_t speed, uint8_t duplex) __banked
// bit 14: SLAVE, bit 13: Multi-Port device, 1: LD Loop timin enableed // bit 14: SLAVE, bit 13: Multi-Port device, 1: LD Loop timin enableed
phy_write(port, PHY_MMD_AN, 0x20, 0x6001); phy_write(port, PHY_MMD_AN, 0x20, 0x6001);
// GBCR (1000Base-T Control Register, MMD 31.0xA412) // GBCR (1000Base-T Control Register, MMD 31.0xA412)
phy_modify(port, PHY_MMD_CTRL, 0xa412, 0x0000, 0x0200); phy_modify(port, PHY_MMD31, 0xa412, 0x0000, 0x0200);
} else if (speed == PHY_SPEED_2G5) { } else if (speed == PHY_SPEED_2G5) {
// Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020) // Multi-GBASE-TBASE-T AN Control 1 Register (MMD 7.0x0020)
// bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD Loop timin enableed // bit 14: SLAVE, bit 13: Multi-Port device, bit 8: 2.5GBit available, 1: LD Loop timin enableed
phy_write(port, PHY_MMD_AN, 0x20, 0x6081); phy_write(port, PHY_MMD_AN, 0x20, 0x6081);
// GBCR (1000Base-T Control Register, MMD 31.0xA412) // GBCR (1000Base-T Control Register, MMD 31.0xA412)
phy_modify(port, PHY_MMD_CTRL, 0xa412, 0x0200, 0x0000); phy_modify(port, PHY_MMD31, 0xa412, 0x0200, 0x0000);
} }
} }
phy_write(port, PHY_MMD_AN, 0x00, 0x3000); // Enable AN phy_write(port, PHY_MMD_AN, 0x00, 0x3000); // Enable AN
@@ -260,13 +260,13 @@ void phy_set_duplex(uint8_t port, uint8_t fullduplex) __banked
phy_read(port, PHY_MMD_AN, 0x00); phy_read(port, PHY_MMD_AN, 0x00);
v = SFR_DATA_U16; v = SFR_DATA_U16;
if (!(v & 0x1000)) { // AN disabled, we are in forced mode if (!(v & 0x1000)) { // AN disabled, we are in forced mode
phy_read(port, PHY_MMD_CTRL, 0xa400); phy_read(port, PHY_MMD31, 0xa400);
v = SFR_DATA_U16; v = SFR_DATA_U16;
if (fullduplex) if (fullduplex)
v |= 0x0100; v |= 0x0100;
else else
v &= 0xfeff; v &= 0xfeff;
phy_write(port, PHY_MMD_CTRL, 0xa400, v); phy_write(port, PHY_MMD31, 0xa400, v);
return; return;
} }
// Disable AN // Disable AN
@@ -296,7 +296,7 @@ void phy_show(uint8_t port) __banked
// The actual PHY speed is in a Realtek propriatary register // The actual PHY speed is in a Realtek propriatary register
print_string("\nLink speed: "); print_string("\nLink speed: ");
phy_read(port, PHY_MMD_CTRL, 0xA434); phy_read(port, PHY_MMD31, 0xA434);
v = SFR_DATA_U16; v = SFR_DATA_U16;
switch(((v & 0x0600) >> 7) | ((v & 0x0030) >> 4)) { switch(((v & 0x0600) >> 7) | ((v & 0x0030) >> 4)) {
case 0: case 0:
@@ -364,7 +364,7 @@ void phy_show(uint8_t port) __banked
default: default:
print_string("Unknown\n"); print_string("Unknown\n");
} }
phy_read(port, PHY_MMD_CTRL, 0xa400); phy_read(port, PHY_MMD31, 0xa400);
v = SFR_DATA_U16; v = SFR_DATA_U16;
print_string("Duplex: "); print_short(v); print_string(" enabled: "); print_string("Duplex: "); print_short(v); print_string(" enabled: ");
if (v & 0x100) if (v & 0x100)
@@ -385,7 +385,7 @@ void phy_show(uint8_t port) __banked
print_string(" 100Base-Half"); print_string(" 100Base-Half");
if (v & 0x0100) if (v & 0x0100)
print_string(" 100Base-Full"); print_string(" 100Base-Full");
phy_read(port, PHY_MMD_CTRL, 0xa412); phy_read(port, PHY_MMD31, 0xa412);
v = SFR_DATA_U16; v = SFR_DATA_U16;
if (v & 0x0200) if (v & 0x0200)
print_string(" 1000Base-Full"); print_string(" 1000Base-Full");
@@ -405,7 +405,7 @@ void phy_show(uint8_t port) __banked
print_string(" 100Base-Half"); print_string(" 100Base-Half");
if (v & 0x0100) if (v & 0x0100)
print_string(" 100Base-Full"); print_string(" 100Base-Full");
phy_read(port, PHY_MMD_CTRL, 0xa414); phy_read(port, PHY_MMD31, 0xa414);
v = SFR_DATA_U16; v = SFR_DATA_U16;
if (v & 0x0400) if (v & 0x0400)
print_string(" 1000Base-Half"); print_string(" 1000Base-Half");
@@ -426,17 +426,17 @@ void phy_show(uint8_t port) __banked
void phy_reset(uint8_t port) __banked void phy_reset(uint8_t port) __banked
{ {
uint16_t v; uint16_t v;
phy_read(port, PHY_MMD_CTRL, 0xa610); phy_read(port, PHY_MMD31, 0xa610);
v = SFR_DATA_U16; v = SFR_DATA_U16;
// If PHY off, do nothing // If PHY off, do nothing
if (v & 0x0800) if (v & 0x0800)
return; return;
// Disable PHY // Disable PHY
phy_write(port, PHY_MMD_CTRL, 0xa610, v | 0x0800); phy_write(port, PHY_MMD31, 0xa610, v | 0x0800);
delay(2); delay(2);
// Re-enable PHY // Re-enable PHY
phy_write(port, PHY_MMD_CTRL, 0xa610, v & 0xf7ff); phy_write(port, PHY_MMD31, 0xa610, v & 0xf7ff);
} }
// Read RTL8224 register. // Read RTL8224 register.
rtl837x_port.c
+1 -1
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@@ -349,7 +349,7 @@ void port_stats_print(void) __banked
write_char('0' + machine.log_to_phys_port[i]); write_char('\t'); write_char('0' + machine.log_to_phys_port[i]); write_char('\t');
if (!machine.is_sfp[i]) { if (!machine.is_sfp[i]) {
phy_read(i, 0x1f, 0xa610); phy_read(i, PHY_MMD31, 0xa610);
if (SFR_DATA_8 == 0x20) if (SFR_DATA_8 == 0x20)
print_string("On\t"); print_string("On\t");
else else
rtlplayground.c
+5 -4
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@@ -18,6 +18,7 @@
#include "uip/uip.h" #include "uip/uip.h"
#include "uip/uip_arp.h" #include "uip/uip_arp.h"
#include "machine.h" #include "machine.h"
#include "phy.h"
extern __code const struct machine machine; extern __code const struct machine machine;
@@ -1598,7 +1599,7 @@ void rtl8373_init(void)
rtl8224_phy_enable(); rtl8224_phy_enable();
// Disable PHYs for configuration // Disable PHYs for configuration
phy_write_mask(0xff,0x1f,0xa610,0x2858); phy_write_mask(0xff,PHY_MMD31,0xa610,0x2858);
// Set bits 0x13 and 0x14 of 0x5fd4 // Set bits 0x13 and 0x14 of 0x5fd4
// r5fd4:0002914a R5fd4-001a914a // r5fd4:0002914a R5fd4-001a914a
@@ -1628,7 +1629,7 @@ void rtl8373_init(void)
// TODO: patch the PHYs // TODO: patch the PHYs
// Re-enable PHY after configuration // Re-enable PHY after configuration
phy_write_mask(0xff,0x1f,0xa610,0x2058); phy_write_mask(0xff,PHY_MMD31,0xa610,0x2058);
// Enables MAC access // Enables MAC access
// Set bits 0xc-0x14 of 0x632c to 0x1f8, see rtl8372_init // Set bits 0xc-0x14 of 0x632c to 0x1f8, see rtl8372_init
@@ -1664,7 +1665,7 @@ void rtl8372_init(void)
reg_write_m(RTL837X_CFG_PHY_MDI_REVERSE); reg_write_m(RTL837X_CFG_PHY_MDI_REVERSE);
// Disable PHYs for configuration // Disable PHYs for configuration
phy_write_mask(0xf0,0x1f,0xa610,0x2858); phy_write_mask(0xf0,PHY_MMD31,0xa610,0x2858);
// Set bits 0x13 and 0x14 of 0x5fd4 // Set bits 0x13 and 0x14 of 0x5fd4
// r5fd4:0002914a R5fd4-001a914a // r5fd4:0002914a R5fd4-001a914a
@@ -1691,7 +1692,7 @@ void rtl8372_init(void)
// TODO: patch the PHYs // TODO: patch the PHYs
// Re-enable PHY after configuration // Re-enable PHY after configuration
phy_write_mask(0xf0,0x1f,0xa610,0x2058); phy_write_mask(0xf0,PHY_MMD31,0xa610,0x2058);
// Enables MAC access // Enables MAC access
// Set bits 0xc-0x14 of 0x632c to 0x1f8, see rtl8372_init // Set bits 0xc-0x14 of 0x632c to 0x1f8, see rtl8372_init